PE64905MLBB-Z datasheet(2/11 Pages) PEREGRINE

2 / 11 page

Product Specification

PE64905

Page 2 of 11

Document No. 70-0335-06 │ UltraCMOS® RFIC Solutions

Parameter

Configuration

Condition

Min

Typ

Max

Units

Operating Frequency Range

Both

100

3000

MHz

Minimum Capacitance

Series

Shunt

State = 00000, 100 MHz (RF+ to RF-)

State = 00000, 100 MHz (RF+ to Grounded RF-)

0.49

0.99

0.60

1.10

0.71

1.21

Maximum Capacitance

Series

Shunt

State = 11111, 100 MHz (RF+ to RF-)

State = 11111, 100 MHz (RF+ to Grounded RF-)

4.09

4.59

4.60

5.10

5.11

5.61

Parasitic Capacitance

Series

All States, 100 MHz (RF+ to GND, RF- to GND)

0.5

Tuning Ratio

Series

Shunt

100 MHz

7.7:1

4.6:1

Step Size

Both

5 bits (32 states), constant step size (100 MHz)

0.129

Equivalent Series Resistance

Series

State = 00000

State = 11111

1.40

1.33

Ω

Quality Factor (Cmin)1

Shunt

100 MHz, with Ls removed

1 GHz, with Ls removed

2 GHz, with Ls removed

3 GHz, with Ls removed

Quality Factor (Cmax)1

Shunt

100 MHz, with Ls removed

1 GHz, with Ls removed

2 GHz, with Ls removed

3 GHz, with Ls removed

Self Resonant Frequency

Shunt

State 00000

State 11111

7.5

3.1

GHz

Harmonics (2fo)2

Series

100 MHz - 3 GHz

-36

dBm

Harmonics (3fo)2

100 MHz - 3 GHz

-36

dBm

Input Intercept Point (2nd Order)

Series

100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing

105

dBm

Input Intercept Point (3rd Order)

Series

100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing

dBm

Switching Time3, 4

Both

50% CTRL to 10/90% delta capacitance between any two

states

µs

Start-up Time3

Both

Time from VDD within specification to all performances within

specification

100

µs

Wake-up Time3, 4

Both

State change from standby mode to RF state to all perfor-

mances within specification

100

µs

Table 1. Electrical Specifications @ 25°C, VDD = 2.6V

Notes: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit.

Q = XC/R = (X-XL)/R, where X = XL+XC , XL = 2*pi*f*L, XC = -1/(2*pi*f*C), which is equal to removing the effect of parasitic inductance LS.

2. In series or shunt between 50Ω ports. Pulsed RF input with 4620

µs period, 50% duty cycle, measured per 3GPP TS 45.005.

3. DC path to ground at RF+ and RF- must be provided to achieve specified performance.

4. State change activated on rising edge of SCL for ACK bit following data word.

PE64905MLBB-Z Datasheet(PDF) 2 Page - Peregrine Semiconductor Corp.

PE64905MLBB-Z Datasheet(HTML) 2 Page - Peregrine Semiconductor Corp.

Html Pages

1 2 3 4 5 6 7 8 9 10 11

Datasheet Download

Link URL