AS2701A datasheet(5/16 Pages) AMSCO

5 / 16 page

AS-Interface Slave IC

AS2701A (ISA3+)

Rev. C, October 2000

Page 5 of 16

Write Cycle

After the device address, the write cycle R/W-Bit=0, necessary for the identification of the write

cycle, is sent. The E

2PROM acknowledges the correct receipt with the acknowledge bit ACK.

Then the data byte which should be written into the E

2PROM reacknowledges with an ACK

signal of the E

2PROM. The STOP condition ends the cycle.

Read Cycle

The read cycle is similar to the herein described write cycle. In this case the R/W-Bit = 1 which

causes the E

2PROM to place read data for the received Byte address on the bus after the

acknowledge.

START

Condition

STOP

Condition

SDA

SCL

The START condition is recognized by the E

2PROM when a H/L edge arises on the dataline

SDA during the high phase of the clock.

The STOP condition is present when a L/H edge arises on the dataline SDA during the high

phase of the clock SCL. The timing of the E

2PROM interface is derived from the AS-Interface

quartz frequency of 5.333 MHz.

AS2701A Datasheet(PDF) 5 Page - ams AG