1.2.2 TX-BPF

The staircase waveform generated by the FG-DAC in combination with the divider by 16 has

to be filtered by an anti-aliasing filter because the SC-Filter clock is not synchronous to the

FSK-signal. There is a 6th order bandpass filter, which is also used as receive-filter in

receive-mode, implemented to reduce the FSK-spectrum. The filter-clock gets canceled by a

smoothing filter at the end of this filter-chain.

Both, AAF and SMF will be designed in a way to move their corner-frequencies according to

the frequency-band programmation. With the help of the resonator built with the transformer

and attached capacitor, the unwanted frequencies (SC-clk, harmonics) are attenuated so that

the signal spectrum at the transformer-output passes the following specification

45

50

55

60

65

70

[dBuV]

75

10k

100k

1M

10M

A: max 56dBuV@150kHz

A

B

C

Unwanted Frequency Components

Limitations (avg. measurement)

B: max 46dbuV >500kHz

C: max 50dBuV >5MHz

1.2.3 Output-Stage

AS5502: The output stage is designed to amplify the FSK-signal by a factor of 7 with the

help of an external buffer-stage to 14Vpp. The transfer from the 5V circuitry (asic) to the 24V

buffer-structure is done by current-source outputs. The on-chip resistor-network is done in a

way to shift the DC-operating point from 2.5V (on chip) to 12V (ext. buffer). With this

output-voltage a transformer with a ratio of 2.5:1 can be used (VLmax=2Vrms). The buffer

gives a very low impedance which is needed to modulate the power-line (Line-impedance: 5

.. 150ohm).

AS5501 is available for 12V buffer-supply

- amplification-factor: 3.5 instead of 7.0

- buffer DC-operating point: 6V instead of 12V

AS5501 / AS5502 Multimode Powerline Modem

Data Sheet

Rev A, May 2000

Page 11/25

Cpll

AVSS

AFCF

10nF