AD14060 datasheet(39/44 Pages) AD

39 / 44 page

AD14060/AD14060L

–39–

REV. A

AD14060/AD14060L ASSEMBLY

RECOMMENDATIONS

SOCKET INFORMATION

Standard sockets and carriers are available for the AD14060/

AD14060L, if needed. Socket part number IC53-3084-262 and

carrier part number ICC-308-1 are available from Yamaichi

Electronics.

Trim and Form

The AD14060/AD14060L will be shipped as shown on the final

page of the data sheet with untrimmed and unformed leads and

with the nonconductive tie bar in place. This avoids disturbance of

lead spacing and coplanarity prior to assembly. Optimally, the

leads should be trimmed, formed and solder-dipped just prior to

placement on the board.

Trim/Form can be accomplished with a Universal Trim/Form,

Customer-Designed Trim/Form, or with the Analog Devices’

Developed Tooling described below.

A trim/form tool specific to the AD14060/AD14060L has been

developed and is available for use by all parties at:

Tintronics Industries

2122-A Metro Circle

Huntsville, AL 35801

205-650-0220

Contact Person: Tom Rice

The package outline and dimensions resulting from this tool are

shown below. (Alternatively, the package can also be trimmed/

formed for cavity-down placement.)

LOAD CAPACITANCE – pF

100

120

Y = 0.0796X + 1.17

Y = 0.0467X + 0.55

RISE TIME

FALL TIME

140

160

180

200

Figure 33. Typical Output Rise Time (10%–90% VDD) vs.

Load Capacitance (VDD = 3.3 V)

LOAD CAPACITANCE – pF

100

120

Y = 0.0391X + 0.36

Y = 0.0305X + 0.24

RISE TIME

FALL TIME

140

160

180

200

Figure 34. Typical Output Rise Time (0.8 V –2.0 V) vs.

Load Capacitance (VDD = 3.3 V)

LOAD CAPACITANCE – pF

–1

200

100

125

150

175

NOMINAL

–0.7

4.5

Y = 0.0329X - 1.65

Figure 35. Typical Output Delay or Hold vs. Load Capaci-

tance (at Maximum Case Temperature) (VDD = 3.3 V)

0.170

(4.318)

2.110 (53.59)

2.210

±0.010 (56.134 ±0.254)

0.016 MIN

0 TO 10 MILS

° TO 8°

DETAIL "A"

AD14060 Datasheet(PDF) 39 Page - Analog Devices

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