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AD14060L Datasheet(PDF) 38 Page - Analog Devices |
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AD14060L Datasheet(HTML) 38 Page - Analog Devices |
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38 / 44 page ![]() AD14060/AD14060L –38– REV. A (per data line). The hold time will be tDECAY plus the minimum disable time (i.e., tHDWD for the write cycle). REFERENCE SIGNAL tDIS OUTPUT STARTS DRIVING VOH (MEASURED) – ∆V VOL (MEASURED) + ∆V tMEASURED VOH (MEASURED) VOL (MEASURED) 2.0V 1.0V VOH (MEASURED) VOL (MEASURED) HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.5V OUTPUT STOPS DRIVING tENA tDECAY Figure 27. Output Enable/Disable +1.5V 50pF TO OUTPUT PIN IOL IOH Figure 28. Equivalent Device Loading for AC Measure- ments (Includes All Fixtures) INPUT OR OUTPUT 1.5V 1.5V Figure 29. Voltage Reference Levels for AC Measure- ments (Except Output Enable/Disable) Capacitive Loading Output delays and holds are based on standard capacitive loads: 50 pF on all pins (see Figure 28). The delay and hold specifica- tions given should be derated by a factor of 1.5 ns/50 pF for loads other than the nominal value of 50 pF. Figures 30 and 31 show how output rise time varies with capacitance. Figure 32 graphically shows how output delays and holds vary with load capacitance. (Note that this graph or derating does not apply to output disable delays; see the previous section Output Disable Time under Test Conditions.) The graphs of Figures 30, 31 and 32 may not be linear outside the ranges shown. LOAD CAPACITANCE – pF 16.0 8.0 0 0 200 20 40 60 80 100 120 140 160 180 14.0 12.0 4.0 2.0 10.0 6.0 3.7 1.1 14.7 7.4 FALL TIME RISE TIME Figure 30. Typical Output Rise Time (10%–90% VDD) vs. Load Capacitance (VDD = 5 V) LOAD CAPACITANCE – pF 0 0 20 40 60 80 100 120 RISE TIME FALL TIME 140 160 180 200 0.5 0.6 1.0 1.5 2.0 2.5 3.0 3.5 1.6 2.9 Figure 31. Typical Output Rise Time (0.8 V –2.0 V) vs. Load Capacitance (VDD = 5 V) LOAD CAPACITANCE – pF 5 –1 25 200 50 75 100 125 150 175 4 3 2 1 NOMINAL –0.7 4.5 Figure 32. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (VDD = 5 V) |
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