AD1881A

–18–

REV. 0

Extended Audio Status and Control Register (Index 2Ah)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

h

A

2h

A

2 h

A

2 h

A

2h

A

2l

r

t

C

/

t

S

o

i

d

u

A

d

e

d

n

e

t

x

El

r

t

C

/

t

S

o

i

d

u

A

d

e

d

n

e

t

x

E

l

r

t

C

/

t

S

o

i

d

u

A

d

e

d

n

e

t

x

E

l

r

t

C

/

t

S

o

i

d

u

A

d

e

d

n

e

t

x

El

r

t

C

/

t

S

o

i

d

u

A

d

e

d

n

e

t

x

EX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XA

R

VA

R

V A

R

V A

R

VA

R

Vh

0

0

0

0h

0

0

0

0

h

0

0

0

0

h

0

0

0

0h

0

0

0

0

Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio

features.

VRA

Variable Rate Audio. VRA = 1 enables Variable Rate Audio mode (sample rate control registers and SLOTREQ

signaling.

PCM DAC Rate Register (Index 2Ch)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

)

h

A

7

(

/

h

C

2)

h

A

7

(

/

h

C

2

)

h

A

7

(

/

h

C

2

)

h

A

7

(

/

h

C

2)

h

A

7

(

/

h

C

2e

t

a

R

C

A

D

M

C

Pe

t

a

R

C

A

D

M

C

P

e

t

a

R

C

A

D

M

C

P

e

t

a

R

C

A

D

M

C

Pe

t

a

R

C

A

D

M

C

P5

1

R

S5

1

R

S

5

1

R

S

5

1

R

S5

1

R

S4

1

R

S4

1

R

S

4

1

R

S

4

1

R

S4

1

R

S3

1

R

S3

1

R

S

3

1

R

S

3

1

R

S3

1

R

S2

1

R

S2

1

R

S

2

1

R

S

2

1

R

S2

1

R

S1

1

R

S1

1

R

S

1

1

R

S

1

1

R

S1

1

R

S0

1

R

S0

1

R

S

0

1

R

S

0

1

R

S0

1

R

S9

R

S9

R

S 9

R

S 9

R

S9

R

S8

R

S8

R

S 8

R

S 8

R

S8

R

S7

R

S7

R

S 7

R

S 7

R

S7

R

S6

R

S6

R

S 6

R

S 6

R

S6

R

S5

R

S5

R

S 5

R

S 5

R

S5

R

S4

R

S4

R

S 4

R

S 4

R

S4

R

S3

R

S3

R

S 3

R

S 3

R

S3

R

S2

R

S2

R

S 2

R

S 2

R

S2

R

S1

R

S1

R

S 1

R

S 1

R

S1

R

S0

R

S0

R

S 0

R

S 0

R

S0

R

Sh

0

8

B

Bh

0

8

B

B

h

0

8

B

B

h

0

8

B

Bh

0

8

B

B

Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample

rates are reset to 48k.

SR[15:0]

Writing to this register allows programming of the sampling frequency from 8 kHz (1B80h) to 48 kHz (BB80h) in

1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the codec

to saturate to 48 kHz if a rate greater than 48 kHz is programmed or to 7.040 kHz if a rate less than 7.040 kHz is

programmed. For all rates, if the value written to the register is supported, that value will be echoed back when read,

otherwise the closest rate supported is returned.

PCM ADC Rate Register (Index 32h)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

)

h

8

7

(

/

h

2

3)

h

8

7

(

/

h

2

3

)

h

8

7

(

/

h

2

3

)

h

8

7

(

/

h

2

3)

h

8

7

(

/

h

2

3e

t

a

R

C

D

A

M

C

Pe

t

a

R

C

D

A

M

C

P

e

t

a

R

C

D

A

M

C

P

e

t

a

R

C

D

A

M

C

Pe

t

a

R

C

D

A

M

C

P5

1

R

S5

1

R

S

5

1

R

S

5

1

R

S5

1

R

S4

1

R

S4

1

R

S

4

1

R

S

4

1

R

S4

1

R

S3

1

R

S3

1

R

S

3

1

R

S

3

1

R

S3

1

R

S2

1

R

S2

1

R

S

2

1

R

S

2

1

R

S2

1

R

S1

1

R

S1

1

R

S

1

1

R

S

1

1

R

S1

1

R

S0

1

R

S0

1

R

S

0

1

R

S

0

1

R

S0

1

R

S9

R

S9

R

S 9

R

S 9

R

S9

R

S8

R

S8

R

S 8

R

S 8

R

S8

R

S7

R

S7

R

S 7

R

S 7

R

S7

R

S6

R

S6

R

S 6

R

S 6

R

S6

R

S5

R

S5

R

S 5

R

S 5

R

S5

R

S4

R

S4

R

S 4

R

S 4

R

S4

R

S3

R

S3

R

S 3

R

S 3

R

S3

R

S2

R

S2

R

S 2

R

S 2

R

S2

R

S1

R

S1

R

S 1

R

S 1

R

S1

R

S0

R

S0

R

S 0

R

S 0

R

S0

R

Sh

0

8

B

Bh

0

8

B

B

h

0

8

B

B

h

0

8

B

Bh

0

8

B

B

Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample

rates are reset to 48k.

SR[15:0]

Writing to this register allows programming of the sampling frequency from 8 kHz (1B80) to 48 kHz (BB80h) in

1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the codecto

saturate to 48 kHz if a rate greater than 48 kHz is programmed, or to 7.040 kHz if a rate less than 7.040 kHz

is programmed. For all rates, if the value written to the register is supported, that value will be echoed back

when read, otherwise the closest rate supported is returned.

Serial Configuration (Index 74h)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

h

4

7h

4

7 h

4

7 h

4

7h

4

7

l

a

i

r

e

Sl

a

i

r

e

S

l

a

i

r

e

S

l

a

i

r

e

Sl

a

i

r

e

S

n

o

i

t

a

r

u

g

i

f

n

o

Cn

o

i

t

a

r

u

g

i

f

n

o

C

n

o

i

t

a

r

u

g

i

f

n

o

C

n

o

i

t

a

r

u

g

i

f

n

o

Cn

o

i

t

a

r

u

g

i

f

n

o

C

T

O

L

ST

O

L

S

T

O

L

S

T

O

L

ST

O

L

S

6

16

16

16

16

1

X

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

Xh

x

0

x

7h

x

0

x

7

h

x

0

x

7

h

x

0

x

7h

x

0

x

7

Note: This register is not reset when the reset register (register 00h) is written.

SLOT16

Enable 16-bit slots.

DRQEN and DxRQx are retained only for compatibility with the AD1819. New controller designs should use the VRA bit in register

2Ah and the request bits in the status address slot instead.

If your system uses only a single AD1881A, you can ignore the register mask and the slave 1/slave 2 request bits. If you write to

this register, write ones to all of the register mask bits.

SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots.