CBTL06DP212

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 2 — 3 November 2011

6 of 18

NXP Semiconductors

CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

8.

Functional description

Refer to Figure 1 “Functional diagram”.

The CBTL06DP212 uses a 3.3 V power supply. All main signal paths are implemented

using high-bandwidth pass-gate technology and are bidirectional. No clock or reset signal

is needed for the multiplexer to function.

The switch position for the main channels is selected using the select signal GPU_SEL.

Additionally, the signal DDC_AUX_SEL selects between AUX and DDC positions for the

DDC / AUX channel. The detailed operation is described in Section 8.1.

8.1 Multiplexer/switch select functions

The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and

DDC_AUX_SEL as described below.

DDC_CLK2

H5

differential I/O

Pair of single-ended terminals for DDC clock and data signals,

path 2, left-side.

DDC_DAT2

J5

differential I/O

AUX+

H2

differential I/O

High-speed differential pair for AUX or single-ended DDC signals,

right-side.

AUX



H1

differential I/O

HPD_1

J2

single-ended I/O

Single ended channel for the HPD signal, path 1, left-side.

HPD_2

H3

single-ended I/O

Single ended channel for the HPD signal, path 2, left-side.

HPDIN

J1

single-ended I/O

Single ended channel for the HPD signal, right-side.

VDD

A2, J4

power supply

3.3 V power supply.

GND

B3, C8,

G2, G8,

H4, H7

ground

Ground.

Table 3.

Symbol

Ball

Type

Description

Table 4.

Multiplexer/switch select control for INn and OUTn channels

GPU_SEL

IN1_n

IN2_n

0

active; connected to OUT_n

high-impedance

1

high-impedance

active; connected to OUT_n

Table 5.

Multiplexer/switch select control for HPD channel

GPU_SEL

HPD_1

HPD_2

0

active; connected to HPDIN

high-impedance

1

high-impedance

active; connected to HPDIN