AD1893

–18–

REV. A

DATA IN/OUT

BCLK_I, BCLK_O

NORMAL MODE

BCLK_I, BCLK_O

INVERTED MODE

L

R_I, LR_O

INPUT

WCLK_I, WCLK_O

INPUT

INPUT

MSB–1 MSB–2 MSB–3

LEFT DATA

RIGHT DATA

LSB+1

LSB

MSB–3

MSB–1 MSB–2

LSB

MSB

MSB

Figure 23. Serial Data Input and Output Timing, Word Clock Triggered Mode

BCLK_I, BCLK_O

NORMAL MODE

BCLK_I, BCLK_O

INVERTED MODE

INPUT

DATA IN/OUT

NO MSB DELAY MODE

MSB–2 MSB–3

LEFT DATA

RIGHT DATA

LSB+1

LSB

MSB–3

MSB–2

LSB

DATA IN/OUT

MSB DELAY MODE

MSB–1 MSB–2

LEFT DATA

LSB

LSB+1

LSB+2

MSB–1 MSB–2

RIGHT DATA

LSB+1

LSB

L

R_I, LR_O

INPUT

MSB

MSB–1

MSB

MSB–1

MSB

MSB

Figure 24. Serial Data Input and Output Timing, Left-Justified Left/Right Clock Triggered Modes

RIGHT DATA

MSB–3

MSB

MSB–1 MSB–2

MSB–2 MSB–3

MSB

MSB–1

LSB+1

LSB

LSB+1

BCLK_I, BCLK_O

NORMAL MODE

BCLK_I, BCLK_O

INVERTED MODE

INPUT

L

R_I, LR_O

INPUT

LEFT DATA

LSB–1

16-BIT CLOCK PERIODS

DATA IN/OUT

16-BIT CLOCK PERIODS

LSB

LSB

Figure 25. Serial Data Input and Output Timing, Right-Justified Left / Right Clock Triggered Mode