REV. 0

AD1958

–6–

Table I. DAC Control Register

Bit 11:10

Bit 9:8

Bit 7

Bit 6

Bit 5:4

Bit 3:2

Bit 1:0

Interpolation

Serial Data

Serial Data

De-Emphasis

SPI Register

Factor

Width

Output Phase

Soft Mute

Format

Filter

Address

00 = 8

×*

00 = 24 Bits

*

0 = Noninverted

*

0 = No Mute

*

00 = I

00 = None

*

01

01 = 4

×

01 = 20 Bits

1 = Inverted

1 = Muted

00 = Right Justified

01 = 44.1 kHz

10 = 2

×

10 = 16 Bits

10 = DSP

10 = 32 kHz

11 = Not Allowed

11 = 16 Bits

11 = Left Justified

11 = 48 kH

z

*Default Setting

Table III. PLL Control Register

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7:6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1:0

PLL2

PLL1

XTAL

SPI

Power-

Power-

Power-

Clock

SCLK1

Frequency

SCLK2

MCLK

Register

Down

Down

Down

Configuration

Select

Double

2

Select

Mode

Address

0 = On

1

0 = On

1

0 = On

1

0 = Mode 0

1

SCLK1 =

Reserved

Reserved

0 = Output

1

11

1 = PD

1 = PD

1 = PD

000: 36.864 MHz

1

Set to 0

Set to 0

1 = Input

100: 24.576 MHz

110: 33.8688 MHz

111: 22.5792 MHz

Other combinations reserved

SCLK2 = 16.9344 MHz

1 = Mode 1

00 = 48 kHz

0 = Normal

0 = 22.5792 MHz

01 = Not

1 =

1 = 512

2

Allowed

2

10 = 32 kHz

11 = 44.1 kHz

NOTES

PLL CLOCK SYSTEM

The PLL clock system is expected to be run from a 27 MHz

master clock supplied by the on-board crystal oscillator or an

external source connected to XIN. With the MCLK mode set

to Output, the 27 MHz clock is buffered out to the MCLK

for the DAC. SCLK0 is always set to 33.8688 MHz. SCLK1 is

intended to be used as a master audio clock and will be a multiple

of the sample rate set in the PLL control register (see Table III).

In Mode 0 (Bit 8), it can be set to 512 or 768 times either

44.1 kHz or 48 kHz. SCLK2 will be 16.3944 MHz (384

44.1 kHz). In Mode 1, SCLK1 can be set to 256, 384, 512,

or 768 times 32 kHz, 44.1 kHz, or 48 kHz. SCLK2 can be

set to a constant 22.5792 MHz (512

There are two loop filter pins, LF0 and LF1. They should each

be bypassed to PVDD by a network consisting of a 33 nF capaci-

tor in series with a 750

Ω resistor, paralleled with a 1.8 nF capacitor.

The 27 MHz Master Clock oscillator should have a crystal cut for

an 18 pF load connected between XIN and XOUT, with 22 pF

capacitors connected from XIN and XOUT to PGND.

Table II. DAC Volume Registers

Bit 15:2

Bit 1:0

Volume

SPI Register Address

14 Bits, Unsigned

00 = Left Volume

14 Bits, Unsigned

10 = Right Volume

Default is full volume

RESET/POWER-DOWN

RESET will set the control registers to their default settings. The

chip should be reset on power-up. After reset is deasserted, the

part will come out of reset on the next rising LRCLK.

SERIAL CONTROL PORT

The AD1958 has an SPI-compatible control port to permit

programming the internal control registers for the PLL and DAC.

The DAC output levels may be independently programmed

by means of an internal digital attenuator adjustable in 16384

linear steps.