AD538

–8–

REV. C

LOG RATIO OPERATION

Figure 14 shows the AD538 configured for computing the log of

the ratio of two input voltages (or currents). The output signal

from B is connected to the summing junction of the output ampli-

fier via two series resistors. The 90.9

Ω metal film resistor effec-

tively degrades the temperature coefficient of the

±3500 ppm/°C

resistor to produce a 1.09 k

Ω +3300 ppm/°C equivalent value.

less than zero (–1.2 V in this case) removing this input from the

transfer function.

The 5 k

Ω potentiometer controls the circuit’s scale factor ad-

justment providing a +1 V per decade adjustment. The output

offset potentiometer should be set to provide a zero output with

25k

25k

LOG

RATIO

100

25k

25k

ANTILOG

LOG

OUTPUT

100

AD538

INTERNAL

VOLTAGE

REFERENCE

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

I

B

+10V

+2V

A

D

C

PWR

GND

SIGNAL

GND

+15V

–15V

IN4148

)

OUTPUT

2k

1%

5k

SCALE

FACTOR

ADJUST

AD589

–1.2V

OPTIONAL

ADJUSTMENT

INPUT

1M

10M

90.9

1%

1k

+3500

ppm/ C

10M

10k

OPTIONAL

ADJUSTMENT

68k

5%

48.7

Figure 14. Log Ratio Circuit

The log ratio circuit shown achieves

±0.5% accuracy in the log

domain for input voltages within three decades of input range:

10 mV to 10 V. This error is not defined as a percent of full-

scale output, but as a percent of input. For example, using a

1 V/decade scale factor, a 1% error in the positive direction at

the INPUT of the log ratio amplifier translates into a 4.3 mV

deviation from the ideal OUTPUT (i.e., 1 V

× log

4.3214 mV). An input error 1% in the negative direction is

slightly different, giving an output deviation of 4.3648 mV.

TWO-QUADRANT DIVISION

The two-quadrant linear divider circuit illustrated in Figure 13

uses the same basic connections as the one-quadrant version.

However, in this circuit the numerator has been offset in the

positive direction by adding the denominator input voltage to it.

The offsetting scheme changes the divider’s transfer function

from:

V

V

Z

V

X









to:

= 10V

+ AV

X

()

= 10 V 1 A +













= 10 A +10 V













where A =

35 k

Ω

25 k

Ω









As long as the magnitude of the denominator input is equal to

or greater than the magnitude of the numerator input, the cir-

cuit will accept bipolar numerator voltages. However, under the

conditions of a 0 V numerator input, the output would incor-

rectly equal +14 V. The offset can be removed by connecting

the +10 V reference through resistors R1 and R2 to the output

section’s summing node I at Pin 9 thus providing a gain of 1.4

at the center of the trimming potentiometer. The pot R2 adjusts

out or corrects this offset, leaving the desired transfer function

25k

25k

LOG

RATIO

100

25k

25k

ANTILOG

LOG

OUTPUT

100

AD538

INTERNAL

VOLTAGE

REFERENCE

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

I

B

+10V

+2V

A

D

C

PWR

GND

SIGNAL

GND

+15V

–15V

IN4148

)

FOR

OUTPUT

R1

12.4k

R2

10k

ZERO

ADJUST

AD589

1M

68k

5%

3.9M

35k

NUMERATOR

10M

–1.2V

OPTIONAL

Z OFFSET TRIM

DENOMINATOR

35k

Figure 13. Two-Quadrant Division with 10 V Scaling