AD5533

–14–

REV. 0

MICROPROCESSOR INTERFACING

AD5533 to ADSP-21xx Interface

The ADSP-21xx family of DSPs are easily interfaced to the

AD5533 without the need for extra logic.

A data transfer is initiated by writing a word to the TX register

after the SPORT has been enabled. In a write sequence data is

clocked out on each rising edge of the DSP’s serial clock and

clocked into the AD5533 on the falling edge of its SCLK. In

readback 16 bits of data are clocked out of the AD5533 on each

rising edge of SCLK and clocked into the DSP on the rising edge

of SCLK. DIN is ignored. The valid 14 bits of data will be cen-

tered in the 16-bit RX register when using this configuration.

The SPORT control register should be set up as follows:

TFSW

= RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

ISCLK

= 1, Internal Serial Clock

TFSR

= RFSR = 1, Frame Every Word

IRFS

= 0, External Framing Signal

ITFS

= 1, Internal Framing Signal

SLEN

= 1001, 10-Bit Data Words (SHA Mode Write)

SLEN

= 1111, 16-Bit Data Words (Readback Mode)

Figure 14 shows the connection diagram.

SCLK

AD5533*

SYNC

DR

TFS

RFS

DT

SCLK

ADSP-2101/

ADSP-2103*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 14. AD5533 to ADSP-2101/ADSP-2103 Interface

AD5533 to MC68HC11

The Serial Peripheral Interface (SPI) on the MC68HC11 is

configured for Master Mode (MSTR = 1), Clock Polarity Bit

(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is

configured by writing to the SPI Control Register (SPCR)—see

68HC11 User Manual. SCK of the 68HC11 drives the SCLK of

SYNC signal is derived from a port line (PC7). When data is

being transmitted to the AD5533, the

SYNC line is taken low

(PC7). Data appearing on the MOSI output is valid on the fall-

ing edge of SCK. Serial data from the 68HC11 is transmitted in

8-bit bytes with only eight falling clock edges occurring in the

transmit cycle. Data is transmitted MSB first. In order to trans-

mit 10-data bits in SHA mode it is important to left-justify the

data in the SPDR register. PC7 must be pulled low to start a

transfer. It is taken high and pulled low again before any further

read/write cycles can take place. A connection diagram is shown in

Figure 15.

SCLK

AD5533*

SYNC

MISO

PC7

SCK

MC68HC11*

*ADDITIONAL PINS OMITTED FOR CLARITY

MOSI

Figure 15. AD5533 to MC68HC11 Interface

AD5533 to PIC16C6x/7x

The PIC16C6x Synchronous Serial Port (SSP) is configured

as an SPI Master with the Clock Polarity bit = 0. This is done

by writing to the Synchronous Serial Port Control Register

(SSPCON). See user PIC16/17 Microcontroller User Manual.

In this example I/O port RA1 is being used to pulse

SYNC and

enable the serial port of the AD5533. This microcontroller trans-

fers only eight bits of data during each serial transfer operation;

therefore, two consecutive read/write operations are needed for

a 10-bit write and a 14-bit readback. Figure 16 shows the con-

nection diagram.

SCLK

PIC16C6x/7x*

SYNC

SCK/RC3

AD5533*

*ADDITIONAL PINS OMITTED FOR CLARITY

SDO/RC5

SDI/RC4

RA1

Figure 16. AD5533 to PIC16C6x/7x Interface

AD5533 TO 8051

The AD5533 requires a clock synchronized to the serial data.

The 8051 serial interface must therefore be operated in Mode

0. In this mode serial data enters and exits through RxD and a

shift clock is output on TxD. Figure 17 shows how the 8051 is

connected to the AD5533. Because the AD5533 shifts data

out on the rising edge of the shift clock and latches data in on

the falling edge, the shift clock must be inverted. The AD5533

requires its data with the MSB first. Since the 8051 outputs

the LSB first, the transmit routine must take this into account.

8051*

SCLK

SYNC

TxD

AD5533*

*ADDITIONAL PINS OMITTED FOR CLARITY

RxD

P1.1

Figure 17. AD5533 to 8051 Interface