AD542/AD544/AD547

REV. B

–10–

This particular log ratio circuit is free from the dynamic prob-

lems that plague many other log circuits. The –3 dB bandwidth

is 50 kHz over the top 3 decades, 100 nA to 100

µA, and de-

creases smoothly at lower input levels. This circuit needs no ad-

ditional frequency compensation for stable operation from

input current sources, such as photodiodes, that may have 100

pF of shunt capacitance. For larger input capacitances a 20 pF

integration capacitor around each amplifier will provide a

smoother frequency response.

This log ratio amplifier can be readily adjusted for optimum

accuracy by following this simple procedure. First, apply V1 =

+1.00 V. Repeat this procedure until gain and balance readings

are within 2 mV of ideal values.

Figure 35. Low Drift Integrator and

Low Leakage Guarded Reset

Figure 34. Differentiator

Figure 36. Wien-Bridge

Figure 37. Capacitance

Multiplier

Figure 38. Long Interval

Timer–1,000 Seconds

Figure 39. Positive Peak Detector