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AD5301 Datasheet(PDF) 15 Page - Analog Devices |
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AD5301 Datasheet(HTML) 15 Page - Analog Devices |
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15 / 20 page  REV. 0 AD5334/AD5335/AD5336/AD5344 –15– DB8 DB9 X X X X HIGH BYTE LOW BYTE X = UNUSED BIT DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 XX Figure 30. Data Format For AD5335 POWER-ON RESET The AD5334/AD5335/AD5336/AD5344 are provided with a power-on reset function, so that they power up in a defined state. The power-on state is: • Normal operation •0 – VREF output range • Output voltage set to 0 V Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. POWER-DOWN MODE The AD5334/AD5335/AD5336/AD5344 have low power con- sumption, dissipating typically 1.5 mW with a 3 V supply and 3 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, which is selected by taking pin PD low. When the PD pin is high, the DACs work normally with a typical power consumption of 600 µA at 5 V (500 µA at 3 V). In power- down mode, however, the supply current falls to 200 nA at 5 V (80 nA at 3 V) when the DACs are powered down. Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the outputs are three-state while the part is in power-down mode, and provides a defined input condition for whatever is connected to the outputs of the DAC amplifiers. The output stage is illustrated in Figure 31. RESISTOR STRING DAC POWER-DOWN CIRCUITRY AMPLIFIER VOUT Figure 31. Output Stage During Power-Down The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs when VDD = 3 V. This is the time from a rising edge on the PD pin to when the output voltage deviates from its power-down volt- age. See Figure 22. Table I. AD5334/AD5336/AD5344 Truth Table CLR LDAC CS WR A1 A0 Function 1 1 1 X X X No Data Transfer 1 1 X 1 X X No Data Transfer 0 X X X X X Clear All Registers 11 0 0 ➝1 0 0 Load DAC A Input Register, GAIN A (AD5334/AD5336) 11 0 0 ➝1 0 1 Load DAC B Input Register, GAIN B (AD5334/AD5336) 11 0 0 ➝1 1 0 Load DAC C Input Register, GAIN C (AD5334/AD5336) 11 0 0 ➝1 1 1 Load DAC D Input Register, GAIN D (AD5334/AD5336) 1 0 X X X X Update DAC Registers X = don’t care. Table II. AD5335 Truth Table CLR LDAC CS WR A1 A0 HBEN Function 1 1 1 X X X X No Data Transfer 1 1 X 1 X X X No Data Transfer 0 X X X X X X Clear All Registers 11 0 0 ➝1 0 0 0 Load DAC A Low Byte Input Register 11 0 0 ➝1 0 0 1 Load DAC A High Byte Input Register 11 0 0 ➝1 0 1 0 Load DAC B Low Byte Input Register 11 0 0 ➝1 0 1 1 Load DAC B High Byte Input Register 11 0 0 ➝1 1 0 0 Load DAC C Low Byte Input Register 11 0 0 ➝1 1 0 1 Load DAC C High Byte Input Register 11 0 0 ➝1 1 1 0 Load DAC D Low Byte Input Register 11 0 0 ➝1 1 1 1 Load DAC D High Byte Input Register 1 0 X X X X X Update DAC Registers X = don’t care. |
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