REV. 0

AD5544/AD5554

–14–

SERIAL DATA INTERFACE

The AD5544/AD5554 uses a 3-wire (

CS, SDI, CLK) SPI com-

patible serial data interface. Serial data of AD5544 and AD5554

is clocked into the serial input register in an 18-bit and 16-bit

data-word format respectively. MSB bits are loaded first. Table

II defines the 18 data-word bits for AD5544. Table III defines

the 16 data-word bits for AD5554. Data is placed on the SDI

pin, and clocked into the register on the positive clock edge of

CLK subject to the data setup and data hold time requirements

specified in the Interface Timing Specifications. Data can only

be clocked in while the

CS chip select pin is active low. For

AD5544, only the last 18 bits clocked into the serial register will

be interrogated when the

CS pin returns to the logic high state,

extra data bits are ignored. For AD5554, only the last 16 bits

clocked into the serial register will be interrogated when the

CS

pin returns to the logic high state. Since most microcontrollers

output serial data in 8-bit bytes, three right-justified data bytes

can be written to the AD5544. Keeping the

CS line low between

the first, second, and third byte transfers will result in a success-

ful serial register update. Similarly, two right-justified data bytes

can be written to the AD5554. Keeping the

CS line low between

the first and second byte transfer will result in a successful serial

register update.

Once the data is properly aligned in the shift register, the posi-

tive edge of the

CS initiates the transfer of new data to the target

DAC register, determined by the decoding of address bits A1

and A0. For AD5544, Tables I, III, V, and Figure 2 define the

characteristics of the software serial interface. For AD5554,

Tables II, IV, V, and Figure 3 define the characteristics of the

software serial interface. Figures 8 and 9 show the equivalent

logic interface for the key digital control pins for AD5544.

AD5554 has similar configuration, except with 14 data bits.

Two additional pins

RS and MSB provide hardware control

over the preset function and DAC Register loading. If these

functions are not needed, the

RS pin can be tied to logic high.

The asynchronous input

RS pin forces all input and DAC regis-

ters to either the zero-code state (MSB = 0), or the half-scale

state (MSB = 1)

INPUT

REGISTER

R

INPUT

REGISTER

R

INPUT

REGISTER

R

INPUT

REGISTER

R

DAC A

B

C

D

2:4

DECODE

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

A0

A1

EN

16

DAC D

REGISTER

R

DAC C

REGISTER

R

DAC B

REGISTER

R

DAC A

REGISTER

R

POWER-

ON

RESET

DAC B

DAC C

DAC D

DAC A

AD5544

DGND

MSB

LDAC

RS

SET

MSB

SET

MSB

SDO

SDI

CLK

CS

Figure 8. System Level Digital Interfacing