REV. 0

AD5330/AD5331/AD5340/AD5341

–8–

AD5341 FUNCTIONAL BLOCK DIAGRAM

BUFFER

12-BIT

DAC

GND

AD5341

PD

DAC

REGISTER

LOW BYTE

REGISTER

HBEN

CS

WR

CLR

LDAC

RESET

POWER-ON

RESET

HIGH BYTE

REGISTER

POWER-DOWN

LOGIC

BUF

GAIN

..

INTER-

FACE

LOGIC

AD5341 PIN FUNCTION DESCRIPTIONS

Pin

No.

Mnemonic

Function

1

HBEN

High Byte Enable Pin. This pin is used when writing to the device to determine if data is written

to the high byte register or the low byte register.

2

BUF

Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.

Reference Input.

Output of DAC. Buffered output with rail-to-rail operation.

5

GND

Ground reference point for all circuitry on the part.

6

CS

Active low Chip Select Input. This is used in conjunction with

WR to write data to the parallel interface.

7

WR

Active Low Write Input. This is used in conjunction with

CS to write data to the parallel interface.

8

GAIN

9

CLR

Asynchronous active low control input that clears all input registers and DAC registers to zero.

10

LDAC

Active low control input that updates the DAC registers with the contents of the input registers.

11

PD

Power-Down Pin. This active low control pin puts the DAC into power-down mode.

12

Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled

with a 10

µF capacitor in parallel with a 0.1 µF capacitor to GND.

13–20

AD5341 PIN CONFIGURATION

TOP VIEW

(Not to Scale)

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

AD5341

LDAC

GAIN

WR

CS

GND

PD

12-BIT

CLR

HBEN

BUF