AD608

REV. B

–7–

THEORY OF OPERATION

The AD608 (Figure 20) consists of a mixer followed by a loga-

rithmic IF strip with RSSI and hard limited outputs. Each sec-

tion will be described below.

Mixer

The mixer is a doubly-balanced modified Gilbert cell mixer. Its

maximum input level for linear operation is

±56.2 mV regard-

less of the impedance across the mixer’s inputs, or –15 dBm for

a 50

Ω input termination. The input impedance of the mixer

can be modeled as a simple parallel RC network; the values ver-

sus frequency are listed in Table I. The bandwidth from the RF

input to the IF output at MXOP pin is –1 dB at 30 MHz and

then falls off rapidly (Figure 4).

Mixer Gain

The mixer’s conversion gain is the product of its transcon-

ductance and the impedance seen at pin MXOP. For a 330

Ω

parallel-terminated filter at 10.7 MHz, the load impedance is

165

Ω, the gain is 24 dB, and the output is 15.85 × 56.2 mV, or

±891 mV, centered on the midpoint of the supply voltage. For

other load impedances, the expression for the gain in dB is

G

0.0961 R

L

()

the load impedance at pin MXOP. The limitations on the

mixer’s gain are the

±6 mA maximum output current at MXOP

and the maximum allowable voltage swing at pin MXOP, which

is

±1.0 V for a 3 V supply or 5 V supply.

Table I. Mixer Input Impedance vs. Frequency

Frequency

Resistance

Capacitance

(MHz)

(Ohms)

(pF)

45

2800

3.1

70

2600

3.1

100

1800

3.1

200

1200

3.1

300

760

3.2

400

520

3.4

500

330

3.6

24dB MIXER GAIN

110dB LIMITER GAIN

90dB RSSI

BIAS

MXOP

MIXER

BPF

DRIVER

VMID

LO

PREAMP

AD608

RFHI

RFLO

IF INPUT

–75dBm TO

IFHI

IFLO

LMOP

VPS2

RSSI

FDBK

COM3

FINAL

LIMITER

100nF

10nF

330

Ω

±50µA

10.7MHz

BANDPASS

FILTER

330

Ω

MID-SUPPLY

IF BIAS

6

5

7

8

10

9

13

14

12

15

11

1

2

3

4

16

LIMITER

OUTPUT

400mVp-p

PRUP

RF INPUT

–95 TO

VPS1 COM1

COM2

LOIP

RSSI OUTPUT

20mV/dB

0.2V TO 1.8V

3dB NOMINAL

INSERTION LOSS

+2.7V TO 5.5V

5-STAGE IF AMPLIFIER

(16dB PER STAGE)

7 FULL-WAVE

RECTIFIER CELLS

≈

≈

+2.7V TO 5.5V

LO INPUT

–16dBm

CMOS LOGIC

INPUT

±6mA MAX OUTPUT

(

±890mV INTO 165Ω)

100

Ω

18nF

1. –15dBm =

±56mV MAX FOR LINEAR OPERATION

2. 39.76mV RMS TO 396.6mV RMS FOR

±1 dB

RSSI ACCURACY

NOTES:

Figure 20. Functional Block Diagram