AD6411

–9–

REV. 0

CONTROLLING THE AD6411 OPERATING MODE

Table IV. Operating Mode Control Register

D15

D14

D13

D12

D11

D10

D9

D8

M0

A4

A3

A2

A1

A0

IF/RSSI RXMixer

D7

D6

D5

D4

D3

D2

D1

D0

DMOD

DIV

CP

TX

UHF

BSW

REGS

1

BUF

VCO

The operating mode register, loaded through the serial port

when the LSB is “1,” allows any circuit block to be indepen-

dently powered on or off. This can be bypassed to enable mode

control of the IC via the three external control lines. Transitions

between major DECT modes can be made with a single word

program (including channel change) when using the serial inter-

face only. Table V defines the bit status for the various IC oper-

ating modes when used with the serial interface only.

Table V. Bit Status for the Different Operating Modes

Data Bits

(D9...D0)

Operating

Mode Register

Function

Comments

00 0000 0101

All Off Mode

All Circuits Off

00 0000 0111

Stand-By Mode

Regulators On

00 0111 1111

Prior to TX Slot

VCO, TX Buffer,

Dividers, Charge Pump,

Regulators Active,

VREF (1.4 V) Active

00 0101 1111

Active TX Slot

VCO, TX Buffer, Di-

viders, Regulator

Circuits Active,

00 1110 1011

Prior to RX Slot

Pump, Regulators, De-

modulator Precharge

Circuits Active,

VREF (1.4 V) Active

11 1100 1011

Active RX Slot

RX Mixer, VCO

ers, Regulators, De-

modulator, Receive

Strip Circuits Active,

VREF (1.4 V) Active

NOTES

mit slot depending on the effect of thermal transients on VCO pulling. In this

mode the dividers are biased but inactive. This can also be implemented when

external control lines are used with bits TXM, RXM1, RXM0.

Low when BSW is high, high when BSW is low. In Table V, band switch

output is high for AcRx and PrRx slots, otherwise it is low.

CHANNEL SELECTION/FREQUENCY CONTROL

The M0 and A4–A0 bits in the operating mode register control

the channel selection for the AD6411 synthesizer. The M0 bit

selects the M Counter division ratio.

M0: M Counter Divide Ratio

M0

Function

0

M Divide Ratio 32

1

M Divide Ratio 34

The A4 through A0 bits control the A counter division ratio,

and control the channel selection. Refer to the section of this

data sheet on Synthesizer Programming for a mapping of chan-

nel frequency to synthesizer divider words.

A4–A0: A Counter Division Ratio

“A”

A4

A3

A2

A1

A0

000000

100001

200010

300011

––––––

30

11110

31

11111

ANALOG/RF INTERFACE DETAILS

The AD6411 is an advanced 1.9 GHz radio transceiver circuit

and requires careful attention to the selection of external com-

ponents. The AD6411 is readily capable of performance that

meets the ETS-300-176-1 (formerly TBR06) DECT radio

specifications. This section of the data sheet will describe sug-

gestions for external componentry that will allow the design of a

complete DECT RF transceiver.

Low Noise Amplifier

An external LNA is required to meet the RF leakage specifica-

tions in ETS-300-176-1. The following circuit, based on a Si-

emens BFP405 discrete transistor, is representative of a suitable

LNA. The SC1.89 SAW filter removes images prior to the down

converter. The filter is matched to the AD6411 input with a

printed inductor and fixed capacitor. Complete details of the

circuit, with transmission-line dimensions, can be found in

Siemens Application Note No. 020.

RF IN

22pF

TL2

TL3

TL1

39k

100pF

100

TL6

10

BFP405

33pF

TL5

10pF

10nF

+3V

RF OUT

TL4

33pF

Figure 4. LNA circuit