Preliminary Technical Information

AD6426

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no

obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent

rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98)

- 34 -

Confidential Information

TIMING SPECIFICATION

Memory Interface

Parameter

Comment ( Timing for 3-state access, see Figure 15 )

Min

Max

Units

Timing Requirement

Control Processor read chip select to data valid

158

ns

Control Processor read address to data valid

162

ns

Control Processor read enable to data valid

129

ns

Control Processor data hold

0

ns

Switching Characteristic

Control Processor write chip select setup

10

ns

Control Processor chip select hold

5

ns

Control Processor write address setup

10

ns

Control Processor address hold

5

ns

Control Processor write pulse width

111

ns

Control Processor data setup

68

ns

Control Processor data hold

15

ns

Control Processor read pulse width

145

ns

WRITE

CS

ADD 15:0

HWR/LWR

DATA15:0

t

10a

READ

CS

ADD15:0

RD

DATA7:0

t

11

t

12a

t

13

t

14

t

15

t

16

t

10b

t

11

t

17

t

12b

t

13

t

19

t

18

Figure 15. Memory Interface Timing