AD6458

–12–

REV. 0

I/Q Convention

The AD6458 is a complete IF receive subsystem. Although not

a requirement for using the AD6458, most applications will use

a high-side LO injection on pin LOIP (Pin 4) of the mixer. The

I and Q convention is such that when a spectrum with I leading

Q is presented to the input of the mixer, and a high-side LO is

presented on pin LOIP, I still leads Q at the baseband output of

the AD6458.

Phase-Locked Loop

The demodulators are driven by quadrature signals provided by

a variable frequency quadrature oscillator (VFQO), phase-

locked to a reference signal applied to Pin FREF. When this

signal is at the IF, in-phase and quadrature baseband outputs

are generated at the I output (IRXP and IRXN) and Q output

(QRXP and QRXN), respectively. The quadrature accuracy of

this VFQO is typically 2

° at 13 MHz. A simplified diagram of

the FREF input is shown in Figure 35.

FREF

50µA PTAT

5k

Ω

20k

Ω

5k

Ω

Figure 35. Simplified Schematic of the FREF Interface

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Lead Plastic SSOP

(RS-20)

20

11

10

1

0.295 (7.50)

0.271 (6.90)

PIN 1

SEATING

PLANE

0.008 (0.203)

0.002 (0.050)

0.07 (1.78)

0.066 (1.67)

0.0256

(0.65)

BSC

0.078 (1.98)

0.068 (1.73)

0.009 (0.229)

0.005 (0.127)

0.037 (0.94)

0.022 (0.559)

8

°

0

°

The VFQO operates from 5 MHz to 50 MHz and is controlled

series RC network, forming the PLL loop filter, is connected

ensures that the frequency-control voltage on pin FLTR re-

mains held during power-down, so reacquisition of the carrier

occurs in less than 80

µs.

In practice, the probability of a phase mismatch at power-up is

high, so the worst-case linear settling period to full lock needs to

be considered in making filter choices. This is typically < 80

µs

for a quadrature phase error of

±3° at an IF of 13 MHz. Note

that the VFQO always provides quadrature between its own I

and Q outputs, but the phasing between it and the reference

carrier will swing around the final value during the PLL’s set-

tling time.

Bias System

°C.

Any voltage from 3.0 V to 3.6 V may be used.

The bias system includes a fast acting active high CMOS-

compatible power-up switch, allowing the part to idle at 1

µA

when disabled. Biasing is generally proportional-to-absolute-

temperature (PTAT) to ensure stable gain with temperature.

Other special biasing techniques are used to ensure very accu-

rate gain, stable over the full temperature range.