AD660

REV. A

–9–

OUTPUT SETTLING AND GLITCH

The AD660’s output buffer amplifier typically settles to within

0.0008% FS (1/2 LSB) of its final value in 8

µs for a full-scale

step. Figures 7a and 7b show settling for a full-scale and an LSB

step, respectively, with a 2 k

Ω, 1000 pF load applied. The guar-

anteed maximum settling time at +25

°C for a full-scale step is

13

µs with this load. The typical settling time for a 1 LSB step is

2.5

µs.

The digital-to-analog glitch impulse is specified as 15 nV-s typi-

cal. Figure 7c shows the typical glitch impulse characteristic at

the code 011 . . . 111 to 100 . . . 000 transition when loading

the second rank register from the first rank register.

20

–10

0

0

+10

10

600

400

200

0

–200

–400

–600

µs

a. –10 V to +10 V Full-Scale Step Settling

5

0

0

600

400

200

–200

–400

–600

µs

1

23

4

b. LSB Step Settling

5

0

0

+10

–10

µs

1

23

4

c. D-to-A Glitch Impulse

Figure 7. Output Characteristics

DIGITAL CIRCUIT DETAILS

The AD660 has several “dual-use” pins which allow flexible op-

eration while maintaining the lowest possible pin count and con-

sequently the smallest package size. The user should, therefore,

pay careful attention to the following information when applying

the AD660.

Data can be loaded into the AD660 in serial or byte mode as

described below.

Serial Mode Operation

is enabled by bringing SER (Pin 17)

low. This changes the function of DB0 (Pin 12) to that of the

serial input pin, SIN. It also changes the function of DB1 (Pin

11) to a control input that tells the AD660 whether the serial

data is going to be loaded MSB or LSB first.

In serial mode HBE and LBE are effectively disabled except for

LBE

’s dual function which is to control whether the user wishes

to have the asynchronous clear function go to unipolar or bipo-

lar zero. (A low on LBE, when CLR is strobed, sends the DAC

output to unipolar zero, a high to bipolar zero.) The AD660

does not care about the status of HBE when in serial mode.

Data is clocked into the input register on the rising edge of CS

as shown in Figure 1b. The data is then resident in the first rank

latch and can be loaded into the DAC latch by taking LDAC

high. This will cause the DAC to change to the appropriate out-

put value.

It should be noted that the clear function clears the DAC latch

but does not clear the first rank latch. Therefore, the data that

was previously resident in the first rank latch can be reloaded

simply by bringing LDAC high after the event that necessitated

CLR

to be strobed has ended. Alternatively, new data can be

loaded into the first rank latch if desired.

The serial out pin (SOUT) can be used to daisy chain several

DACs together in multi-DAC applications to minimize the

number of isolators being used to cross an intrinsic safety bar-

rier. The first rank latch simply acts like a 16-bit shift register,

and repeated strobing of CS will shift the data out through

SOUT and into the next DAC. Each DAC in the chain will

require its own LDAC signal unless all of the DACs are to be

updated simultaneously.

Byte Mode Operation

is enabled simply by keeping SER high,

which configures DB0–DB7 as data inputs. In this mode HBE

and LBE are used to identify the data as either the high byte or

low byte of the 16-bit input word. (The user can load the data,

in any order, into the first rank latch.) As in the serial mode

case, the status of LBE, when CLR is strobed determines

whether the AD660 clears to unipolar or bipolar zero. There-

fore, when in byte mode, the user must take care to set LBE to

the desired status before strobing CLR. (In serial mode the user

can simply hardware LBE to the desired state.)

NOTE: CS is edge triggered. HBE, LBE and LDAC are level

triggered.