MJD112 MJD117

3

Motorola Bipolar Power Transistor Device Data

Figure 3. Thermal Response

t, TIME OR PULSE WIDTH (ms)

1

0.01

1000

0.3

0.2

0.07

R

θJC(t) = r(t) RθJC

R

θJC = 6.25°C/W

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1

TJ(pk) – TC = P(pk) θJC(t)

P(pk)

t1

t2

DUTY CYCLE, D = t1/t2

0.01

0.7

0.5

0.1

0.05

0.03

0.02

0.02 0.03

0.05

0.1

0.2 0.3

0.5

1

2

3

5

10

20

30

50

100

200 300

500

0.2

SINGLE PULSE

D = 0.5

0.05

0.1

0.01

Figure 4. Maximum Rated Forward Biased

Safe Operating Area

Figure 5. Power Derating

2

VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)

0.3

100

5

2

0.5

0.2

BONDING WIRE LIMITED

THERMAL LIMIT

SECOND BREAKDOWN LIMIT

5

20

3

TJ = 150°C

CURVES APPLY BELOW RATED VCEO

100

µs

1 ms

dc

0.1

1

3

7

10

10

7

30

25

25

T, TEMPERATURE (

°C)

0

50

75

100

125

150

20

15

10

5

2.5

0

2

1.5

1

0.5

TA TC

TA

SURFACE

MOUNT

TC

0.7

5 ms

50

70

200

500

µs

ACTIVE–REGION SAFE–OPERATING AREA

There are two limitations on the power handling ability of a

transistor: average junction temperature and second break-

down. Safe operating area curves indicate IC – VCE limits of

the transistor that must be observed for reliable operation;

i.e., the transistor must not be subjected to greater dissipa-

tion than the curves indicate.

The data of Figures 5 and 6 is based on TJ(pk) = 150_C; TC

is variable depending on conditions. Second breakdown

pulse limits are valid for duty cycles to 10% provided TJ(pk)

< 150

_C. TJ(pk) may be calculated from the data in Figure 4.

At high case temperatures, thermal limitations will reduce the

power that can be handled to values less than the limitations

imposed by second breakdown.

VR, REVERSE VOLTAGE (VOLTS)

Cib

0.04

30

1

4

10

40

TC = 25°C

200

10

50

70

100

0.1

2

6

20

20

PNP

NPN

0.6

0.4

0.2

0.06

Figure 6. Capacitance

Cob