AD678

REV. C

–6–

PIN DESCRIPTION

28-Lead DIP 44-Lead

Symbol

Pin No.

JLCC Pin No. Type

Name and Function

AGND

7

11

P

Analog Ground. This is the ground return for AIN only.

AIN

6

10

AI

Analog Signal Input.

BIPOFF

10

15

AI

Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight binary

Ω resistor for ±5 V input bipolar mode

and twos complement binary output coding. See Figures 7 and 8.

CS

4

6

DI

Chip Select. Active LOW.

DGND

14

23

P

Digital Ground

DB11–DB4

26–19

40, 39, 37, 36,

DO

Data Bits 11 through 4. In 12-bit format (see 12/

8 pin), these pins provide the upper 8 bits

35, 34, 33, 31

of data. In 8-bit format, these pins provide all 12 bits in two bytes (see R/

L pin).

Active HIGH.

DB3, DB2

18, 17

30, 27

DO

Data Bits 3 and 2. In 12-bit format, these pins provide Data Bit 3 and Data Bit 2.

DB1 (R/

L)

16

26

DO

In 12-bit format, Data Bit 1. Active HIGH.

DB0 (

HBE)

15

25

DO

In 12-bit format, Data Bit 0. Active HIGH.

EOC

27

42

DO

End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH when the

conversion is finished. In asynchronous mode, EOC is an open drain output and

requires an external 3 k

Ω pull-up resistor. See EOCEN and SYNC pins for information

on EOC gating.

EOCEN

1

1

DI

End-Of-Convert Enable. Enables EOC pin. Active LOW.

HBE (DB0)

15

25

DI

In 8-bit format, High Byte Enable. If LOW, output contains high byte. If HIGH, output

contains low byte.

OE

2

3

DI

Output Enable. The falling edge of

OE enables DB11–DB0 in 12-bit format and

DB11–DB4 in 8-bit format. Gated with

CS. Active LOW.

9

14

AI

Reference Input. +5 V input gives 10 V full-scale range.

8

12

AO

Ω resistor for normal operation.

R/

L (DB1)

16

26

DI

In 8-bit format, Right/Left justified. Sets alignment of 12-bit result within 16-bit field.

SC

3

5

DI

Start Convert. Active LOW. See SYNC pin for gating.

SYNC

13

21

DI

by

CS. If tied to DGND (asynchronous mode), SC and EOCEN are independent of CS,

and EOC is an open drain output. EOC requires an external 3 k

Ω pull-up resistor in

asynchronous mode.

11

17

P

+12 V Analog Power.

5

8

P

–12 V Analog Power.

28

43

P

+5 V Digital Power.

12/

8

12

19

DI

Twelve/eight-bit format. If tied HIGH, sets output format to 12-bit parallel. If tied

LOW, sets output format to 8-bit multiplexed.

No Connect

2, 4, 7, 9, 13,

16, 18, 20, 22,

24, 28, 29, 32,

38, 41, 44

Type: AI = Analog Input; AO = Analog Output; DI = Digital Input (TTL and 5 V CMOS compatible); DO = Digital Output (TTL and 5 V CMOS compatible).

All DO pins are three-state drivers; P = Power.

PIN CONFIGURATIONS

DIP PACKAGE

JLCC PACKAGE

EOCEN

OE

AIN

AGND

SC

CS

BIPOFF

12/

8

SYNC

DGND

13

18

1

2

28

27

5

6

7

24

23

22

3

4

26

25

8

21

920

10

19

11

12

17

16

14

15

TOP VIEW

(Not to Scale)

AD678

EOC

DB9

DB8

DB7

DB11

DB10

DB6

DB5

DB4

DB3

DB2

DB1 (R/

L)

DB0 (

HBE)

6

5

4

3

2

44 43 42 41 40

18 19 20 21 22

24 25 26 27 28

23

7

8

9

10

11

12

13

14

15

16

17

39

38

37

36

35

34

33

32

31

30

29

PIN 1

IDENTIFIER

TOP VIEW

NC

NC

NC

NC

AIN

AGND

BIPOFF

NC

NC

NC

DB9

DB8

DB7

DB10

DB6

DB5

DB4

DB3

AD678

NC = NO CONNECT