AD73311LARS datasheet(13/36 Pages) AD

13 / 36 page

REV. A

AD73311L

–13–

Table X. Control Word Description

8765

432

Device Address

Control

Frame

Description

Bit 15

Control/

Data

When set high, it signiﬁes a control word in Program or Mixed Program/Data Modes. When

set low, it signiﬁes a data word in Mixed Program/Data Mode or an invalid control word in

Program Mode.

Bit 14

Read/

Write

When set low, it tells the device that the data ﬁeld is to be written to the register selected by

the register ﬁeld setting provided the address ﬁeld is zero. When set high, it tells the device

that the selected register is to be written to the data ﬁeld in the input serial register and that

the new control word is to be output from the device via the serial output.

Bits 13–11

Device Address

This 3-bit ﬁeld holds the address information. Only when this ﬁeld is zero is a device selected.

If the address is not zero, it is decremented and the control word is passed out of the device

via the serial output.

Bits 10–8

This 3-bit ﬁeld is used to select one of the ﬁve control registers on the AD73311L.

Bits 7–0

This 8-bit ﬁeld holds the data that is to be written to or read from the selected register provided

the address ﬁeld is zero.

Table IX. Control Register Map

Address (Binary)

Name

Description

Type

Width

Reset Setting (Hex)

000

CRA

Control Register A

0x00

001

CRB

Control Register B

0x00

010

CRC

Control Register C

0x00

011

CRD

Control Register D

0x00

100

CRE

Control Register E

0x00

101

CRF

Control Register F

0x00

110 to 111

Reserved

Table VIII. DAC Timing Control

DA4

DA3

DA2

DA1

DA0

Time Advance

000000 ns

00001

488.2 ns

00010

976.5 ns

——————

11110

14.64

µs

11111

15.13

µs

*DMCLK = 16.384 MHz.

OPERATION

Resetting the AD73311L

The pin

RESET resets all the control registers. All registers are

reset to zero indicating that the default SCLK rate (DMCLK/8)

and sample rate (DMCLK/2048) are at a minimum to ensure

that slow speed DSP engines can communicate effectively. As

well as resetting the control registers using the

RESET pin, the

device can be reset using the

RESET bit (CRA:7) in Control

cycles. On reset, DATA/

PGM (CRA:0) is set to 0 (default condi-

tion) thus enabling Program Mode. The reset conditions ensure

that the device must be programmed to the correct settings after

power-up or reset. Following a reset, the SDOFS will be asserted

2048 DMCLK cycles after

RESET going high. The data that

is output following

RESET and during Program Mode is ran-

dom and contains no valid information until either Data or

Mixed Mode is set.

Power Management

The individual functional blocks of the AD73311L can be

enabled separately by programming the power control register

CRC. It allows certain sections to be powered down if not

required, which adds to the device’s flexibility in that the user

need not incur the penalty of having to provide power for a

certain section if it is not necessary to their design. The power

control register provides individual control settings for the major

functional blocks and also a global override that allows all sec-

tions to be powered up by setting the bit. Using this method the

user could, for example, individually enable a certain section,

such as the reference (CRC:5), and disable all others. The glo-

bal power-up (CRC:0) can be used to enable all sections but if

power-down is required using the global control, the reference

will still be enabled, in this case, because its individual bit is set.

Refer to Table XIII for details of the settings of CRC.

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