AD73360 datasheet(13/35 Pages) AD

13 / 35 page

REV. A

AD73360

–13–

Serial Port (SPORT)

The AD73360s communicate with a host processor via the

bidirectional synchronous serial port (SPORT) which is compat-

ible with most modern DSPs. The SPORT is used to transmit

and receive digital data and control information. Multiple

AD73360s be cascaded together (up to a limit of eight) to pro-

vide additional input channels.

In both transmit and receive modes, data is transferred at the

serial clock (SCLK) rate with the MSB being transferred first.

Due to the fact that the SPORT of each AD73360 block uses a

common serial register for serial input and output, communica-

tions between an AD73360 and a host processor (DSP engine)

must always be initiated by the AD73360s themselves. In this

configuration the AD73360s are described as being in Master

mode. This ensures that there is no collision between input data

and output samples.

SPORT Overview

The AD73360 SPORT is a flexible, full-duplex, synchronous

serial port whose protocol has been designed to allow up to

eight AD73360 devices to be connected in cascade, to a single

DSP via a six-wire interface. It has a very flexible architecture

that can be configured by programming two of the internal

control registers in each device. The AD73360 SPORT has

three distinct modes of operation: Control Mode, Data Mode

and Mixed Control/Data Mode.

NOTE: As each AD73360 has its own SPORT section, the

registers which control SPORT and sample rate operation (CRA

and CRB) must be programmed with the same values, otherwise

incorrect operation may occur.

In Program Mode (CRA:0 = 0), the device’s internal configura-

tion can be programmed by writing to the eight internal control

registers. In this mode, control information can be written to or

read from the AD73360. In Data Mode (CRA:0 = 1), any infor-

mation that is sent to the device is ignored, while the encoder

section (ADC) data is read from the device. In this mode, only

ADC data is read from the device. Mixed mode (CRA:0 = 1

and CRA:1 = 1) allows the user to send control information and

receive either control information or ADC data. This is achieved

by using the MSB of the 16-bit frame as a flag bit. Mixed mode

reduces the resolution to 15 bits with the MSB being used to

indicate whether the information in the 16-bit frame is control

information or ADC data.

The SPORT features a single 16-bit serial register that is used

for both input and output data transfers. As the input and out-

put data must share the same register there are some precau-

tions that must be observed. The primary precaution is that no

information must be written to the SPORT without reference to

an output sample event, which is when the serial register will be

overwritten with the latest ADC sample word. Once the SPORT

starts to output the latest ADC word, it is safe for the DSP to

write new control words to the AD73360. In certain configura-

tions, data can be written to the device to coincide with the

output sample being shifted out of the serial register—see section

on interfacing devices. The serial clock rate (CRB:2–3) defines

how many 16-bit words can be written to a device before the

next output sample event will happen.

The SPORT block diagram, shown in Figure 9, details the blocks

associated with AD73360 including the eight control registers

(A–H), external MCLK to internal DMCLK divider and serial

clock divider. The divider rates are controlled by the setting of

Control Register B. The AD73360 features a master clock

divider that allows users the flexibility of dividing externally

available high frequency DSP or CPU clocks to generate a lower

frequency master clock internally in the AD73360 which may be

more suitable for either serial transfer or sampling rate require-

ments. The master clock divider has five divider options (

÷1

default condition,

÷2, ÷3, ÷4, ÷5) that are set by loading the

master clock divider field in Register B with the appropriate

code (see Table VI). Once the internal device master clock

(DMCLK) has been set using the master clock divider, the

sample rate and serial clock settings are derived from DMCLK.

MCLK

DIVIDER

MCLK

(EXTERNAL)

RESET

SDIFS

SDI

SERIAL PORT

(SPORT)

SERIAL REGISTER

SCLK

CONTROL

DMCLK

(INTERNAL)

SDOFS

SDO

CONTROL

SCLK

DIVIDER

Figure 9. SPORT Block Diagram

The SPORT can work at four different serial clock (SCLK)

rates: chosen from DMCLK, DMCLK/2, DMCLK/4 or

DMCLK/8, where DMCLK is the internal or device master

clock resulting from the external or pin master clock being di-

vided by the master clock divider. Care should be taken when

selecting Master Clock, Serial Clock and Sample Rate divider

settings to ensure that there is sufficient time to read all the data

from the AD73360 before the next sample interval.

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