PCAL9535A datasheet(9/46 Pages) NXP

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PCAL9535A

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Product data sheet

Rev. 1 — 28 September 2012

9 of 46

NXP Semiconductors

PCAL9535A

Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O

6.2.6 Output drive strength register pairs (40h, 41h, 42h, 43h)

The Output drive strength registers control the output drive level of the GPIO. Each GPIO

can be configured independently to a certain output current level by two register control

bits. For example, Port 0.7 is controlled by register 41 bits CC0.7 (bits [7:6]), Port 0.6 is

controlled by register 41 CC0.6(bits [5:4]). The output drive level of the GPIO is

programmed 00b = 0.25

, 01b = 0.50, 10b = 0.75, or 11b = 1 of the maximum drive

capability of the I/O. See Section 8.2 “Output drive strength control”. A register pair write is

described in Section 7.1 and a register pair read is described in Section 7.2.

6.2.7 Input latch register pair (44h, 45h)

The input latch registers (registers 44 and 45) enable and disable the input latch of the I/O

pins. These registers are effective only when the pin is configured as an input port. When

an input latch register bit is 0, the corresponding input pin state is not latched. A state

change of the corresponding input pin generates an interrupt. A read of the input register

clears the interrupt. If the input goes back to its initial logic state before the input port

When an input latch register bit is 1, the corresponding input pin state is latched. A change

of state in the input generates an interrupt and the input logic value is loaded into the

corresponding bit of the input port register (registers 0 and 1). A read of the input port

port register is read, then the interrupt is not cleared and the corresponding bit of the input

port register keeps the logic value that initiated the interrupt. See Figure 12 “Read input

port register (latch enabled), scenario 3”.

For example, if the P0_4 input was as logic 0 and the input goes to logic 1 then back to

logic 0, the input port 0 register will capture this change and an interrupt is generated (if

unmasked). When the read is performed on the input port 0 register, the interrupt is

Table 13.

Current control port 0 register (address 40h)

Bit

Symbol

CC0.3

CC0.2

CC0.1

CC0.0

Default

Table 14.

Current control port 0 register (address 41h)

Bit

Symbol

CC0.7

CC0.6

CC0.5

CC0.4

Default

Table 15.

Current control port 1 register (address 42h)

Bit

Symbol

CC1.3

CC1.2

CC1.1

CC1.0

Default

Table 16.

Current control port 1 register (address 43h)

Bit

Symbol

CC1.7

CC1.6

CC1.5

CC1.4

Default

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