AD7676AST datasheet(14/20 Pages) AD

14 / 20 page

REV. 0

AD7676

–14–

RESET

DATA

BUSY

CNVST

Figure 12. RESET Timing

For other applications, conversions can be automatically initi-

ated. If CNVST is held low when BUSY is low, the AD7676

controls the acquisition phase and then automatically initiates a

new conversion. By keeping CNVST low, the AD7676 keeps

the conversion process running by itself. It should be noted that

the analog input has to be settled when BUSY goes low. Also, at

power-up, CNVST should be brought low once to initiate the

conversion process. In this mode, the AD7676 could sometimes

run slightly faster than the guaranteed limit of 500 kSPS.

DIGITAL INTERFACE

The AD7676 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel data bus. The

AD7676 digital interface also accommodates both 3 V or 5 V

logic by simply connecting the OVDD supply pin of the AD7676

to the host system interface digital supply. Finally, by using the

OB/2C input pin, either two’s complement or straight binary

coding can be used.

The two signals CS and RD control the interface. When at least

one of these signals is high, the interface outputs are in high

impedance. Usually, CS allows the selection of each AD7676 in

multi-circuits applications and is held low in a single AD7676

design. RD is generally used to enable the conversion result on

the data bus.

CNVST

BUSY

DATA

BUS

CS = RD = 0

PREVIOUS CONVERSION DATA

NEW DATA

t10

t11

Figure 13. Master Parallel Data Timing for Reading

(Continuous Read)

PARALLEL INTERFACE

The AD7676 is configured to use the parallel interface (Figure 13)

when the SER/PAR is held low. The data can be read either

after each conversion, which is during the next acquisition

phase, or during the following conversion as shown, respectively,

in Figure 14 and Figure 15. When the data is read during the

conversion, however, it is recommended that it be read-only

during the first half of the conversion phase. That avoids any

potential feedthrough between voltage transients on the digital

interface and the most critical analog conversion circuitry.

DATA

BUS

t12

t13

BUSY

CURRENT

CONVERSION

Figure 14. Slave Parallel Data Timing for Reading

(Read after Convert)

CS = 0

CNVST,

CONVERSION

DATA

BUS

t12

t13

BUSY

Figure 15. Slave Parallel Data Timing for Reading (Read

During Convert)

The BYTESWAP pin allows a glueless interface to an 8-bit bus.

As shown in Figure 16, the LSB byte is output on D[7:0] and

the MSB is output on D[15:8] when BYTESWAP is low. When

BYTESWAP is high, the LSB and MSB bytes are swapped and

the LSB is output on D[15:8] and the MSB is output on D[7:0].

By connecting BYTESWAP to an address line, the 16-bit data

can be read in two bytes on either D[15:8] or D[7:0].

BYTE

PINS D[15:8]

PINS D[7:0]

HI-Z

HIGH BYTE

LOW BYTE

HIGH BYTE

HI-Z

t12

t13

Figure 16. 8-Bit Parallel Interface

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