AD7731BN datasheet(28/44 Pages) AD

28 / 44 page

AD7731

–28–

REV. 0

FASTStep™ Mode (SKIP = 0, FAST = 1)

The second mode of operation of the second stage filter is in

FASTStep™ mode which enables it to respond rapidly to step

inputs even when the second stage filter is in the loop. The

FASTStep™ mode is not relevant with SKIP mode enabled.

The FASTStep™ mode is enabled by placing a 1 in the FAST

bit of the Filter Register. If the FAST bit is 0, the part continues

to process step inputs with the normal FIR filter as the second

stage filter. With FASTStep™ mode enabled, the second stage

filter will continue to process steady state inputs with the filter

in its normal FIR mode of operation. However, the part is con-

tinuously monitoring the output of the first stage filter and com-

paring it with the second-previous output. If the difference

between these two outputs is greater than a predetermined

threshold (1% of full scale), the second stage filter switches to a

simple moving average computation. This also happens when a

change in channels takes place regardless of how close the volt-

ages on the two channels are. When the change is detected, the

STDY bit of the Status Register goes to 1.

The initial number of averages in the moving average computa-

tion is either 2 (chop enabled) or 1 (chop disabled). The num-

ber of averages will be held at this value as long as the threshold

is exceeded. Once the threshold is no longer exceeded (the step

on the analog input has settled), the number of outputs used to

compute the moving average output is increased. The first and

second outputs from the first stage filter where the threshold is

no longer exceeded is computed as an average by 2, then 4

outputs with an average of 4, 8 outputs with an average of 8 and

6 outputs with an average of 16. At this time, the second stage

filter reverts back to its normal FIR mode of operation. When

the second stage filter reverts back to the normal FIR, the

STDY

bit of the Status Register goes to 0.

Figure 13 gives an indication of the different responses to a step

input with FASTStep™ mode enabled and disabled. The verti-

cal axis indicates the settling of the output to the input step

change while the horizontal axis shows how many outputs it

takes for that settling to occur. The positive input step change

occurs at a time coincident with the fifth output.

NUMBER OF OUTPUTS

20000000

15000000

025

10000000

5000000

Figure 13. Step Response for FASTStep™ and Normal

Operation

In FASTStep™ mode, the part has settled to the new value

much faster. For example, with CHP = 1, the FASTStep™

mode settles to its value in two outputs while the normal mode

settling takes 23 outputs. Between the second and 23rd output,

the FASTStep™ mode produces a settled result but with addi-

tional noise compared to the specified noise level for its operat-

ing conditions. This noise level starts at approximately 3 times

the final noise converging to FIR mode performance. The com-

plete settling time to where the part is back within the specified

noise number, is the same for FASTStep™ mode and for normal

mode. When switching channels, the profile of Figure 13 will

not be seen. Since the part is synchronized when a channel

change takes place, it will not produce an output until the filter

(either FASTStep™ or FIR) is settled. Table XVIII gives an

indication of the faster settling time benefits of FASTStep™

mode.

As can be seen from Table XVIII, the FASTStep™ mode gives

a much earlier indication of where the output channel is going

and what its new value is. This feature is very useful in scanning

multiple channels where the user does not have to wait for the

FIR settling time to see if a channel has changed value. In this

case, the part can be set up with CHP = 1, SKIP = 0 and FAST

= 1. This takes advantage of the low drift, better noise immunity

benefits of the CHOP mode. When a change in channels takes

place, the part enters FASTStep™ mode and provides an output

result in 2

× 1/Output Rate.

Note, if the FAST bit is set and the part operated in single con-

version mode, the AD7731 will continue to output results until

the

STDY bit goes to 0.

Table XVIII. Time to First and Subsequent Outputs Follow-

ing Channel Change

Time

Time to

SKIP

CHP

FAST

to First O/P

Subsequent O/Ps

× SF/f

MOD

SF/fMOD

× SF/f

MOD

× SF/f

MOD

× SF/f

MOD

SF/fMOD

× SF/f

MOD

× SF/f

MOD

× SF/f

MOD

SF/fMOD

× SF/f

MOD

× SF/f

MOD

1This O/P is fully settled.

2X = Don’t Care.

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