Electronic Components Datasheet Search
  English  ▼

X  

AD7769AP Datasheet(PDF) 6 Page - Analog Devices

Part # AD7769AP
Description  LC2MOS Analog I/O Port
PDF  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7769AP Datasheet(HTML) 6 Page - Analog Devices

Back Button AD7769AP Datasheet HTML 2Page - Analog Devices AD7769AP Datasheet HTML 3Page - Analog Devices AD7769AP Datasheet HTML 4Page - Analog Devices AD7769AP Datasheet HTML 5Page - Analog Devices AD7769AP Datasheet HTML 6Page - Analog Devices AD7769AP Datasheet HTML 7Page - Analog Devices AD7769AP Datasheet HTML 8Page - Analog Devices AD7769AP Datasheet HTML 9Page - Analog Devices AD7769AP Datasheet HTML 10Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 16 page
background image
AD7769
–6–
REV. A
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
1VDD
+12 V Power Supply. This powers the analog circuitry.
2VCC
+5 V Power Supply. This powers the logic circuitry.
3–10
DB7–DB0
Input/Output Data Bus. A bidirectional data port from which ADC output data may be read
and to which DAC input data may be written. DB7 is the Most Significant Bit.
11
INT
Interrupt Output (active low).
INT is set high on the falling edge of RD or WR to the ADC
and goes low at the end of a conversion.
12
CLK
Clock input. A clock is required for the ADC. An external TTL-compatible clock may be applied to
this input pin. Alternatively, tying this pin to VDD enables the internal clock oscillator. With an
external clock, the mark-space ratio can vary from 30/70 to 70/30.
13
CHA/CHB
Channel A/Channel B Select Input. Selects Channel A or Channel B of the DAC or ADC.
Used in conjunction with
WR, RD, CS and ADC/DAC for read or write operations.
14
DGND
Digital Ground.
15
ADC/DAC
ADC or DAC Select Input. Selects either the ADC or the DAC for read or write operations in
conjunction with
WR, RD, CS and CHA/CHB.
16
WR
Write Input (edge triggered). This is used in conjunction with the
ADC/DAC, CHA/CHB and CS
control inputs to start an ADC conversion or write data to the DAC. An ADC conversion starts on the
rising edge of
WR.
17
RD
Read Input (active low). This input must be low to access data from the ADC.
18
CS
Chip Select Input (active low). The device is selected when this input is low.
19
VSWING (ADC)
ADC Reference Input. The voltage applied to this pin with respect to AGND (ADC) sets the
in put voltage Full-Scale Range (FSR) of the ADC. VIN (FSR) = 2 VSWING (ADC).
20
AGND (ADC)
ADC Analog Ground.
21
VINB
Analog Input for Channel B. See VINA description.
22
VBIAS (ADC)
ADC Reference Input. The voltage applied to this pin with respect to AGND (ADC) sets the
midpoint of the ADC transfer function.
23
VINA
Analog Input for Channel A. The input voltage range of both ADC channels is given by:
VIN A/B = VBIAS (ADC)
±V
SWING (ADC).
24
AGND (DAC)
DAC Analog Ground.
25
VSWING (DAC)
DAC Reference Input. The voltage applied to this pin with respect to AGND (DAC) sets the
output voltage Full-Scale Range (FSR) of the DACs. VOUT (FSR) = 2 VSWING (DAC).
26
VOUTB
Analog Output Voltage from DAC B. See VOUTA description.
27
VBIAS (DAC)
DAC Reference Input. The voltage applied to this pin with respect to AGND (DAC) sets the
midpoint output voltage of the DACs.
28
VOUTA
Analog Output Voltage from DAC A. The output voltage range of both DACs is given by:
VOUT A/B = VBIAS (DAC) ± VSWING (DAC).
TERMINOLOGY
Relative Accuracy
For an ADC, Relative Accuracy or endpoint nonlinearity is the
maximum deviation, in LSBs, of the ADC’s actual code transi-
tion points from a straight line drawn between the endpoints of
the ADC transfer function, i.e., the 00 to 01 and FE to FF Hex
(01111111 to 11111111 Binary) code transitions.
For a DAC, Relative Accuracy or endpoint nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer func-
tion, i.e., those voltages which correspond to codes 00 and FF
Hex.
For the specified input and output ranges, 1 LSB = 19.5 mV,
but will vary with VSWING. For both DACs and ADC,
1 LSB = 2 VSWING /256 = FSR/256.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of
±1 LSB max en-
sures monotonicity (DAC) or no missed codes (ADC).
Bias Offset Error
For an ideal ADC, the output code for an input voltage equal to
VBIAS (ADC), should be 80 Hex (10000000 binary). The ADC
Bias Offset Error is the difference between the actual midpoint
voltage for code 80 Hex and VBIAS (ADC), expressed in LSBs.
For an ideal DAC, the output voltage for code 80 Hex should
be equal to VBIAS (DAC). The DAC Bias Offset Error is the
difference between the actual output voltage and VBIAS (DAC),
expressed in LSBs.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com