AD7823

–8–

REV. B

POWER-UP TIMES

The AD7823 has a 1

connected, the AD7823 is in a low current mode of operation.

In order to carry out a conversion, the AD7823 must first be

powered up. The ADC is powered up by a rising edge on the

CONVST pin. A conversion is initiated on the falling edge of

CONVST. Figure 12 shows how to power up the AD7823 when

using the

CONVST pin.

Care must be taken to ensure that the

CONVST pin of the

CONVST

1 s

MODE 1 (

CONVST IDLES HIGH)

CONVST

MODE 2 (

CONVST IDLES LOW)

1µs

1 s

Figure 12. Power-Up Times

POWER VS. THROUGHPUT RATE

By operating the AD7823 in Mode 2, the average power con-

sumption of the AD7823 decreases at lower throughput rates.

Figure 13 shows how the automatic power-down is imple-

mented using the

CONVST signal to achieve the optimum

power performance for the AD7823. The AD7823 is operated

in Mode 2. As the throughput rate is reduced, the device re-

mains in its power-down state for longer, and the average power

consumption over time drops accordingly.

100 s @ 10kSPS

CONVST

4.5 s

POWER-DOWN

1 s

Figure 13. Automatic Power-Down

For example, if the AD7823 is operated in a continuous

sampling mode with a throughput rate of 10 kSPS, the power

consumption is calculated as follows. The power dissipation

up time is 1

µs and the conversion time is 4.5 µs, then the

AD7823 can be said to dissipate 10.5 mW for 5.5

µs (worst

case) during each conversion cycle. If the throughput rate is

10 kSPS, the cycle time is 100

µs, and the average power

dissipated during each cycle is (5.5/100)

× (10.5 mW) = 570 µW.

Figure 2 shows a graph of Power vs. Throughput.

OPERATING MODES

Mode 1 Operation (High Speed Sampling)

When the AD7823 is used in this mode of operation, the part is

not powered down between conversions. This mode of opera-

tion allows high throughput rates to be achieved. The timing

diagram in Figure 14 shows how this optimum throughput rate

is achieved by bringing the

CONVST signal high before the end

of the conversion. The AD7823 leaves its tracking mode and

goes into hold on the falling edge of

CONVST. A conversion is

also initiated at this time and takes 4

µs typ to complete. At this

point, the result of the current conversion is latched into the

serial shift register, and the state of the

CONVST signal is

checked. The

CONVST signal should be high at the end of the

conversion to prevent the part from powering down.

A

B

CONVST

SCLK

CURRENT CONVERSION

RESULT

Figure 14. Mode 1 Operation Timing

The serial port on the AD7823 is enabled on the rising edge of

the

CONVST signal–see Serial Interface section. As explained

earlier, this rising edge should occur before the end of the

conversion process if the part is not to be powered down. A

serial read can take place at any stage after the rising edge of

CONVST. If a serial read is initiated before the end of the

current conversion process (i.e., at time “A”), then the result of

possible to allow the serial read to extend beyond the end of a

conversion. In this case, the new data will not be latched into

the output shift register until the read has finished. If the user

waits until the end of the conversion process, i.e., 4

µs typ after

falling edge of

CONVST (Point “B”), before initiating a read,

the current conversion result is shifted out.