AD7829BN datasheet(15/20 Pages) AD

15 / 20 page

AD7822/AD7825/AD7829

–15–

REV. B

Interfacing Multiplexer Address Inputs

Figure 26 shows a simplified interfacing scheme between the

AD7825/AD7829 and any microprocessor or microcontroller,

which facilitates easy channel selection on the ADCs. The mul-

tiplexer address is latched on the falling edge of the RD signal,

as outlined in the Parallel Interface section, which allows the use

of the 3 LSBs of the address bus to select the channel address.

As shown in Figure 26, only address bits A3 to A15 are address

decoded allowing A0 to A2 to be changed according to desired

channel selection without affecting chip selection.

AD7825/

AD7829

DB7–DB0

A15–A3

DB0–DB7

A15–A3

A2–A0

ADC I/O ADDRESS

MUX ADDRESS

A/D RESULT

MUX ADDRESS

(CHANNEL SELECTION A0–A2)

LATCHED

MICROPROCESSOR READ CYCLE

ADDRESS

DECODE

Figure 26. AD7825/AD7829 Simplified Microinterfacing Scheme

CONVST

EOC

DB7–DB0

AD7822

DSP/

LATCH/ASIC

CONVST

EOC

DB0–DB7

A/D RESULT

Figure 27. AD7822 Stand-Alone Operation

AD7822 Stand–Alone Operation

The AD7822, being the single channel device, does not have

any multiplexer addressing associated with it and can in fact be

controlled with just one signal, i.e., the CONVST signal. As

shown in Figure 27, the RD and CS pins are both tied to the

EOC pin, and the resulting signal may be used as an interrupt

request signal (IRQ) on a DSP, as a WR signal to memory, or as

a CLK to a latch or ASIC. The timing for this interface,

as shown in Figure 27, demonstrates how with the CONVST

signal alone, a conversion may be initiated, data is latched out,

and the operating mode of the AD7822 can be selected.

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