AD7886

–13–

REV. B

POWER SUPPLY CONNECTIONS

The PC board requires two analog power supplies and one 5 V

digital supply. Connections to the analog supply are made di-

rectly to the PC board as shown on the silkscreen in Figure 24.

The connections are labeled V+ and V–, and the range for both

of these supplies is 12 V to 15 V. Connection to the 5 V digital

supply is made through either of the two connectors (SKT3 or

SKT4). The +5 V analog supplies required by the AD7886 are

generated from voltage regulators on the V– and V+ power

supplies.

LINK OPTIONS

There are five link options, labeled LK1 to LK5, which must be

set before using the board.

LK1 Input Range Select

The AD7886 can accommodate three possible analog input

ranges: 0 V to 5 V, 0 to 10 V and +5 V. The link options are as

follows:

0 V to 5 V

Use Link C

0 V to 10 V

Use Link B

±5 V

Use Link A

LK2 and LK3 Control Input Options

The evaluation board includes two latches to increase the data

access time when interfacing to the faster DSP machines. If

DB11

DB4

DB0

DB3

O/P

O/P

SUM

IN

OUT

GND

+V

78L05

IC5

CONVST

BUSY

CS

RD

GND

GND

CLK

CLK

D0

D7

D0

D1

D2

D3

Q7

Q0

74HC374

IC8

74HC374

IC9

D7

D4

Q7

Q0

SKT3

96-WAY

CONNECTOR

IN

OUT

GND

79L05

IC6

V

SS

–V

VIN1

LK5

CONVST

LK2

LK3

LK4

A31

DMD15

B11

DMD8

B18

EDMACK

ECE6 (OUT1)

OUT2

C22

B6

DMD7

DMD0

B20

B27

C11

EIRQ0

A9

C12

CS

RD

C14

C13

CONVST

DIGITAL

GND

A32/B32/

C32

V

SS

+

–

–V

V

OUT

+V

IN

GND

AD586

IC3

AD707

AGND

DGND

ANALOG

INPUT

AD845

–V

+V

–

+

C2

0.1

µF

C1

10

µF

C3

10

µF

C4

0.1

µF

C9/C17

10

µF

C10/C18

0.1

µF

+V

C6

0.1

µF

C5

10

µF

C15

10

µF

C16

0.1

µF

+V

C13

10

µF

C14

0.1

µF

C11

10

µF

C10

0.1

µF

C7

10

µF

C8

0.1

µF

C19

10

µF

C20

0.1

µF

C23

0.1

µF

IC1

AD7886

IC4

IC2

SKT2

SKT1

VIN2

A

B

C

LK1

V

DD

AGND

5V

+

5V

+

5V

+

5V

+

5V

+

V

DD

5REF

+

5V

–

Figure 23. Data Acquisition Circuit Using the AD7886

these latches are not required, they may be removed and the

data digital paths shorted out, i.e., latch inputs Dx shorted to

outputs Qx using wire links in the latch sockets. When using the

latches, the AD7886 control inputs,

CS and RD, must be tied

low via links 2 and 3. The latches are updated by the rising edge

of the

BUSY signal at the end of every conversion. Data is then

read by asserting the latch output enable signals. The alternative

is to remove the latches and assert the ADC’s control inputs

from either of the connectors, SKT3 or SKT4, as outlined in

the data sheet.

Latches Included

Latches Removed

Insert Link 2

Remove Link 2

Insert Link 3

Remove Link 3

LK4 Analog Input Option

LK4 connects the analog input to a component grid or to a

buffer amplifier that drives the ADC input.

LK5

Data format can be 16-bits parallel or two bytes for 8-bit pro-

cessors. There are two data enable controls for the 74HC374

latches, labeled

OUT1 and OUT2. OUT1 enables the 8 MSBs

(IC8), and

OUT2 enables the 4 LSBs (IC9). Link options are:

for 16-bit format, include LK5, for a two byte read format,

remove LK5.