AD8012

–13–

REV. A

Choosing the Appropriate Turns Ratio for the Transformer

Increasing the peak-to-peak output signal from the amplifier in

the previous example, combined with a variation in the turns

ratio of the transformer, can yield further enhancements to the

circuit. The output signal swing of the AD8012 can be increased

to about

±3.9 V before clipping occurs. This increases the peak-

to-peak output of the differential amplifier to 15.6 V. Because

the signal applied to the primary winding is now bigger, the

transformer turns ratio of 1:1 can be replaced with a (step-

down) turns ratio of about 1.3:1 (from amplifier to line). This

steps the 7.8 V peak-to-peak primary voltage down to 6 V. This

is the same secondary voltage as before so the resulting power

delivered to the line is the same.

The received signal, which is small relative to the transmitted

signal, will, however be stepped up by a factor of 1.3. Amplifying

the received signal in this manner enhances its signal-to-noise

ratio and is useful when the received signal is small compared to

the to-be-transmitted signal.

The impedance reflected from the 135

Ω line now becomes

228

amplifier must now drive a total load of 456

Ω (114 Ω + 114 Ω

+ 228

Ω), considerably less than the original 270 Ω load. This

reduces the drive current from the op amps by about 40%.

More significant however is the reduction in dynamic power

consumption; that is, the power the amplifier must consume in

order to deliver the load power. Increasing the output signal so

that it is as close as possible to the power rails, minimizes the

power consumed in the amplifier.

There is, however, a price to pay in terms of increased signal

distortion. Increasing the output signal of each op amp from the

original

±3 V to ±3.9 V reduces the Spurious Free Dynamic

Range (SFDR) from –65 dB to –50 dB (measured at 500 kHz),

even though the overall load impedance has increased from

270

Ω to 456 Ω.

LAYOUT CONSIDERATIONS

The specified high speed performance of the AD8012 requires

careful attention to board layout and component selection.

Table I shows recommended component values for the AD8012

and Figures 44–49 show recommended layouts for the 8-lead

SOIC and microSOIC packages for a positive gain. Proper RF

design techniques and low parasitic component selections are

mandatory.

Table I. Typical Bandwidth vs. Gain Setting Resistors

Small Signal –3 dB BW (MHz),

Gain

–1

750

Ω

750

Ω

53.6

Ω

110

+1

750

Ω

–

49.9

Ω

350

+2

750

Ω

750

Ω

49.9

Ω

150

+10

750

Ω

82.5

Ω

49.9

Ω

40

Ω characteristic input impedance.

The PCB should have a ground plane covering all unused por-

tions of the component side of the board to provide a low im-

pedance ground path. The ground plane should be removed

from the area near the input pins to reduce stray capacitance.

Chip capacitors should be used for supply bypassing (see Fig-

ure 43). One end should be connected to the ground plane

and the other within 1/8 in. of each power pin. An additional

(4.7

µF–10 µF) tantalum electrolytic capacitor should be con-

nected in parallel.

The feedback resistor should be located close to the inverting

input pin in order to keep the stray capacitance at this node to a

minimum. Capacitance greater than 1.5 pF at the inverting

input will significantly affect high speed performance when

operating at low noninverting gains.

Stripline design techniques should be used for long signal traces

(greater than about 1 in.). These should be designed with the

proper system characteristic impedance and be properly termi-

nated at each end.

0.1 F

INVERTING CONFIGURATION

10 F

NONINVERTING CONFIGURATION

0.1 F

10 F

+

+

Figure 43. Inverting and Noninverting Configurations