AD8036-EB datasheet(16/23 Pages) AD

16 / 23 page

REV. A

–16–

AD8036/AD8037

Operation of the AD8036 for negative input voltages and nega-

tive clamp levels on VL is similar, with comparator CL control-

ling S1. Since the comparators see the voltage on the +VIN pin

as their common reference level, then the voltage VH and VL are

defined as “High” or “Low” with respect to +VIN. For example,

if VIN is set to zero volts, VH is open, and VL is +1 V, compara-

tor CL will switch S1 to “C,” so the AD8036 will buffer the

voltage on VL and ignore +VIN.

The performance of the AD8036 and AD8037 closely matches

the ideal just described. The comparator’s threshold extends

from 60 mV inside the clamp window defined by the voltages on

VL and VH to 60 mV beyond the window’s edge. Switch S1 is

implemented with current steering, so that A1’s +input makes a

continuous transition from say, VIN to VH as the input voltage

traverses the comparator’s input threshold from 0.9 V to 1.0 V

for VH = 1.0 V.

The practical effect of these nonidealities is to soften the

transition from amplification to clamping modes, without com-

promising the absolute clamp limit set by the CLAMPIN cir-

cuit. Figure 73 is a graph of VOUT vs. VIN for the AD8036 and a

typical output clamp amplifier. Both amplifiers are set for G =

+1 and VH = +1 V.

The worst case error between VOUT (ideally clamped) and VOUT

(actual) is typically 18 mV times the amplifier closed-loop gain.

This occurs when VIN equals VH (or VL). As VIN goes above

and/or below this limit, VOUT will settle to within 5 mV of the

ideal value.

In contrast, the output clamp amplifier’s transfer curve typically

will show some compression starting at an input of 0.8 V, and

can have an output voltage as far as 200 mV over the clamp

limit. In addition, since the output clamp in effect causes the

amplifier to operate open loop in clamp mode, the amplifier’s

output impedance will increase, potentially causing additional

errors.

The AD8036’s and AD8037’s CLAMPIN input clamp architec-

ture works only for noninverting or follower applications and,

since it operates on the input, the clamp voltage levels VH and

VL, and input error limits will be multiplied by the amplifier’s

140

A B C

0 1 0

1 0 0

0 0 1

VIN > VH

VL ≤ VIN ≤ VH

VIN < VL

–VIN

+VIN

VOUT

Figure 72. AD8036/AD8037 Clamp Amp System

CL– pF

Figure 71. Recommended RSERIES vs. Capacitive Load

INPUT CLAMPING AMPLIFIER OPERATION

The key to the AD8036 and AD8037’s fast, accurate clamp and

amplifier performance is their unique patent pending CLAMPIN

input clamp architecture. This new design reduces clamp errors

by more than 10

× over previous output clamp based circuits, as

well as substantially increasing the bandwidth, precision and

versatility of the clamp inputs.

Figure 72 is an idealized block diagram of the AD8036 con-

nected as a unity gain voltage follower. The primary signal path

comprises A1 (a 1200 V/

µs, 240 MHz high voltage gain, differ-

ential to single-ended amplifier) and A2 (a G = +1 high current

gain output buffer). The AD8037 differs from the AD8036 only

in that A1 is optimized for closed-loop gains of two or greater.

The CLAMPIN section is comprised of comparators CH and

CL, which drive switch S1 through a decoder. The unity-gain

buffers in series with +VIN, VH, and VL inputs isolate the input

pins from the comparators and S1 without reducing bandwidth

or precision.

The two comparators have about the same bandwidth as A1

(240 MHz), so they can keep up with signals within the useful

bandwidth of the AD8036. To illustrate the operation of the

CLAMPIN circuit, consider the case where VH is referenced to

+1 V, VL is open, and the AD8036 is set for a gain of +1, by

connecting its output back to its inverting input through the rec-

ommended 140

Ω feedback resistor. Note that the main signal

path always operates closed loop, since the CLAMPIN circuit

only affects A1’s noninverting input.

If a 0 V to +2 V voltage ramp is applied to the AD8036’s +VIN

for the connection just described, VOUT should track +VIN per-

fectly up to +1 V, then should limit at exactly +1 V as +VIN con-

tinues to +2 V.

In practice, the AD8036 comes close to this ideal behavior. As

the +VIN input voltage ramps from zero to 1 V, the output of the

high limit comparator CH starts in the off state, as does the out-

put of CL. When +VIN just exceeds VIN (ideally, by say 1

µV,

practically by about 18 mV), CH changes state, switching S1

from “A” to “B” reference level. Since the + input of A1 is now

connected to VH, further increases in +VIN have no effect on the

AD8036’s output voltage. In short, the AD8036 is now operat-

ing as a unity-gain buffer for the VH input, as any variation in

VH, for VH > 1 V, will be faithfully reproduced at VOUT.

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