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AD8138ARM Datasheet(PDF) 12 Page - Analog Devices

Part # AD8138ARM
Description  Low Distortion Differential ADC Driver
PDF  16 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD8138ARM Datasheet(HTML) 12 Page - Analog Devices

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REV. E
–12–
AD8138
HIGH PERFORMANCE ADC DRIVING
The circuit in Figure 6 shows a simplified front-end connection
for an AD8138 driving an AD9224, a 12-bit, 40 MSPS A/D
converter. The ADC works best when driven differentially, which
minimizes its distortion as described in its data sheet. The AD8138
eliminates the need for a transformer to drive the ADC and
performs single-ended-to-differential conversion, common-mode
level-shifting, and buffering of the driving signal.
The positive and negative outputs of the AD8138 are connected
to the respective differential inputs of the AD9224 via a pair of
49.9
W resistors to minimize the effects of the switched-capacitor
front end of the AD9224. For best distortion performance, it is
run from supplies of
±5 V.
The AD8138 is configured with unity gain for a single-ended
input-to-differential output. The additional 23
W, 523 W total, at
the input to –IN is to balance the parallel impedance of the 50
W
source and its 50
W termination that drives the noninverting input.
The signal generator has a ground-referenced, bipolar output,
i.e., it drives symmetrically above and below ground. Connecting
VOCM to the CML pin of the AD9224 sets the output common-
mode of the AD8138 at 2.5 V, which is the midsupply level for
the AD9224. This voltage is bypassed by a 0.1
mF capacitor.
The full-scale analog input range of the AD9224 is set to 4 V p-p,
by shorting the SENSE terminal to AVSS. This has been deter-
mined to be the scaling to provide minimum harmonic distortion.
For the AD8138 to swing at 4 V p-p, each output swings 2 V p-p
while providing signals that are 180 out of phase. With a
common-mode voltage at the output of 2.5 V, this means that
each AD8138 output will swing between 1.5 V and 3.5 V.
A ground-referenced 4 V p-p, 5 MHz signal at DIN+ was used
to test the circuit in Figure 6. When the combined-device circuit
was run with a sampling rate of 20 MSPS, the SFDR (spurious-
free dynamic range) was measured at –85 dBc.
49.9
0.1pF
523
499
49.9
499
499
VINB
+5V
DRVDD
AVDD
AVSS
DRVSS
VINA
0.1pF
0.1pF
DIGITAL
OUTPUTS
+5V
AD9224
VOCM
AD8138
–5V
SENSE CML
50
SOURCE
+
49.9
Figure 6. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS A/D Converter



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