REV. 0

–12–

AD823

The first pole in the denominator is the dominant pole of the

amplifier, and occurs at about 18 Hz. This equals the input

stage output impedance R1 multiplied by the Miller-multiplied

value of C1. The second pole occurs at the unity-gain band-

width of the output stage, which is 23 MHz. This type of archi-

tecture allows more open loop gain and output drive to be

obtained than a standard two-stage architecture would allow.

OUTPUT IMPEDANCE

The low frequency open loop output impedance of the

common-emitter output stage used in this design is approxi-

mately 30 k

Ω. While this is significantly higher than a typical

emitter follower output stage, when connected with feedback

the output impedance is reduced by the open loop gain of the

op amp. With 109 dB of open loop gain the output impedance

is reduced to less than 0.2

Ω. At higher frequencies the output

impedance will rise as the open loop gain of the op amp drops;

however, the output also becomes capacitive due to the integra-

tor capacitors C1 and C2. This prevents the output impedance

from ever becoming excessively high (see Figure 17), which can

cause stability problems when driving capacitive loads. In fact,

the AD823 has excellent cap-load drive capability for a high fre-

quency op amp. Figure 33 shows the AD823 connected as a fol-

lower while driving 470 pF direct capacitive load. Under these

conditions the phase margin is approximately 20

°. If greater

phase margin is desired a small resistor can be used in series

with the output to decouple the effect of the load capacitance

from the op amp (see Figure 25). In addition, running the part

at higher gains will also improve the capacitive load drive capa-

bility of the op amp.

S1N

C1

S1P

C5

R1

R1

C2

R2

Figure 36. Small Signal Schematic

APPLICATION NOTES

INPUT CHARACTERISTICS

In the AD823, n-channel JFETs are used to provide a low

offset, low noise, high impedance input stage. Minimum input

rail will cause a loss of amplifier bandwidth and increased

common-mode voltage error.

The AD823 does not exhibit phase reversal for input voltages

input. The input and output are superimposed. The output

The reduced bandwidth above a 4 V input causes the rounding

resistor in series with the AD823’s plus input will prevent phase

reversal, at the expense of greater input voltage noise. This is il-

lustrated in Figure 37b.

GND

10

90

100

0%

1V

2

µs

1V

+V

S

GND

10

90

100

0%

1V

1V

10µs

1V

+5V

V

IN

R

P

V

OUT

AD823

Figure 37. AD823 Input Response