AD824

REV. A

–5–

WAFER TEST LIMITS

Parameter

Symbol

Conditions

Limit

Units

Offset Voltage

1.0

mV max

Input Bias Current

12

pA max

Input Offset Current

20

pA

Input Voltage Range

–0.2 to 3.0

V min

Common-Mode Rejection Ratio

CMRR

66

dB min

Power Supply Rejection Ratio

PSRR

V = + 2.7 V to +12 V

70

µV/V

Large Signal Voltage Gain

Ω

15

V/mV min

Output Voltage High

µA

4.975

V min

Output Voltage Low

25

mV max

Supply Current/Amplifier

∞

600

µA max

NOTE

Electrical tests and wafer probe to the limits shown. Due to variations in assembly

methods and normal yield loss, yield after packaging is not guaranteed for

standard product dice. Consult factory to negotiate specifications based on dice

lot qualifications through sample lot assembly and testing.

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD824 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±18 V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .

±30 V

Output Short Circuit Duration to GND . . . . . . . . . Indefinite

Storage Temperature Range

N, R Package . . . . . . . . . . . . . . . . . . . . . . –65

°C to +150°C

Operating Temperature Range

AD824A, B . . . . . . . . . . . . . . . . . . . . . . . . –40

°C to +85°C

Junction Temperature Range

N, R Package . . . . . . . . . . . . . . . . . . . . . . –65

°C to +150°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300

°C

Package Type

θ

JA

2

θ

JC

Units

14-Pin Plastic DIP (N)

76

33

°C/W

14-Pin SOIC (R)

120

36

°C/W

16-Pin SOIC (R)

92

27

°C/W

NOTES

otherwise noted.

2

θ

for P-DIP packages;

θ

package.

ORDERING GUIDE

Temperature

Model

Range

Package Option

AD824AN

–40

°C to +85°C

14-Pin Plastic DIP

AD824BN

–40

°C to +85°C

14-Pin Plastic DIP

AD824AR

–40

°C to +85°C

14-Pin SOIC

AD824AR-3V

–40

°C to +85°C

14-Pin SOIC

AD824AN-3V

–40

°C to +85°C

14-Pin Plastic DIP

AD824AR-14

–40

°C to +85°C

14-Pin SOIC

AD824AR-14-3V

–40

°C to +85°C

14-Pin SOIC

AD824AR-16

–40

°C to +85°C

16-Pin SOIC

AD824AChips

+25

°C

DICE

DICE CHARACTERISTICS

AD824 Die Size 0.70 X 0.130 inch, 9,100 sq. mils.

Substrate (Die Backside) Is Connected to V+. Transistor

Count, 143.

I6

R1

R2

R9

R7

R17

R14

R12

R13

R15

I5

Q18

Q29

Q27

Q21

Q20

Q23

Q25

Q24

Q31

Q28

Q22

Q19

Q7

Q6

Q5

Q8

Q3

Q2

Q4

I1

I2

I3

I4

+IN

J1

–IN

C1

Q26

J2

C3

C2

C4

Figure 1. Simplified Schematic of 1/4 AD824