AD8361

–14–

REV. A

using the equations:

GAIN

VV

VV

OUT

OUT

IN

IN

=

−

()

−

()

21

21

V

V

GAIN

V

OS

OUT

IN

=−

×

()

11

This can be seen by inserting data from Figures 14 and 17 (con-

plots are consistent with Figures 10 and 11 which show that the

error due to temperature drift decreases with increasing input

level. This results from the offset error having a diminishing

influence with increasing level on the overall measurement error.

From Figure 14, the average Intercept drift is 0.43 mV/

°C from

–40

°C to +25°C and 0.17 mV/°C from +25°C to +85°C. For a

less rigorous compensation scheme, the average drift over the

complete temperature range can be calculated:

DRIFT

V

C

VV

CC

VOS

/

..

°

−−

()

+° − − °

()













0 010

0 028

85

40

= 0.000304 V/

°C

Table V. Evaluation Board Configuration Options

Component

Function

Default Condition

TP1, TP2

Ground and Supply Vector Pins.

Not Applicable

SW1

SW1 = B

the AD8361 is in power-down mode. In Position B, the PWDN pin is grounded,

putting the device in operating mode.

SW2/SW3

Operating Mode. Selects either Ground Referenced Mode, Internal Reference

SW2 = A, SW3 = B

Mode or Supply Reference Mode. See Table I for more details.

(Ground Reference Mode)

C1, R2

Input Coupling. The 75

Ω resistor in position R2 combines with the AD8361’s

R2 = 75

Ω (Size 0402)

internal input impedance to give a broadband input impedance of around 50

Ω.

C1 = 100 pF (Size 0402)

For more precise matching at a particular frequency, R2 can be replaced by a

different value (see Input Matching and Figure 39).

Capacitor C1 ac-couples the input signal and creates a high-pass input filter

whose corner frequency is equal to approximately 8 MHz. C1 can be increased

for operation at lower frequencies. If resistive attenuation is desired at the input,

series resistor R1, which is nominally 0

Ω, can be replaced by an appropriate value.

C2, C3, R6

Power Supply Decoupling. The nominal supply decoupling of 0.01

µF and

C2 = 0.01

µF (Size 0402)

100 pF. A series inductor or small resistor can be placed in R6 for additional

C3 = 100 pF (Size 0402)

decoupling.

R6 = 0

Ω (Size 0402)

C5

Filter Capacitor. The internal 50 pF averaging capacitor can be augmented

C5 = 1 nF (Size 0603)

by placing a capacitance in C5.

C4, R5

Output Loading. Resistors and capacitors can be placed in C4 and R5 to

C4 = R5 = Open

load test V rms.

(Size 0603)

V

GAIN

V

V

DRIFT

TEMP

C

OUT

IN

OS

VOS

=×

×

− °

()

25

The equation can be rewritten to yield a temperature compen-

V

V

V

DRIFT

TEMP

C

GAIN

IN

OUT

OS

VOS

=

−−

×

− °

()

()

25

EVALUATION BOARD

Figures 43 and 46 show the schematic of the AD8361 evalua-

tion board. Note that uninstalled components are drawn in as

dashed. The layout and silkscreen of the component side are

shown in Figures 44, 45, 47, and 48. The board is powered by a

single supply in the range, 2.7 V to 5.5 V. The power supply

is decoupled by 100 pF and 0.01

µF capacitors. Additional

decoupling, in the form of a series resistor or inductor in R6,

can also be added. Table V details the various configuration

options of the evaluation board.