AD9483SLASHPCB datasheet(14/26 Pages) AD

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AD9483

–14–

REV. A

ADC Gain Control

Each of the three ADC channels has independent limited gain

control. The full-scale signal amplitude for a given ADC is set by

the dc voltage on its VREF In pin. The equation relating the full

scale amplitude to VREF In is as follows: FS = (0.4)

× (VREF

IN). The three ADCs are optimized for a full-scale signal ampli-

tude of 1 V, but will accommodate up to

±10% variation.

ADC Offset Control

The offset for each of the three ADCs can be independently

controlled. For a single-ended analog input where the analog

input is connected to a reference, offset can be adjusted simply

by adjusting the dc voltage of the reference. For differential

analog inputs, the user must provide the offset in their signal.

Offset can be adjusted up or down as far as the common-mode

input range will allow.

Power Dissipation

Power dissipation for the AD9483 has two components, VCC

and VDD. Power dissipation from VCC is relatively constant for a

given supply voltage, whereas power dissipation from VDD can

vary greatly. VCC supplies power to the analog circuity. VDD

supplies power to the digital outputs and can be approximated

by the following equation:

P (VDD) = 1/2 C

× V2 × F × N

C = Output Load Capacitance

V =VDD Supply Voltage

F = Encode Frequency

N = Number of Outputs Switching

Nominally, C = 10 pF, V = 3.3 V, F = 140 MSPS, and N = 26.

N comes from the 24 output bits plus two clock outputs, P(VDD) =

197 mW.

Power-Down

The power-down function allows users to reduce power dissipa-

tion when output data is not required. A TTL/CMOS HIGH

signal on pin 76, (PD), shuts down most of the chip and brings

the total power dissipation to less than 100 mW. The internal

bandgap voltage reference remains active during power-down

mode to minimize reactivation time. If the power-down function

is not desired, the PD pin should be tied to ground or held to a

TTL/CMOS LOW level.

Bandgap Voltage Reference

The AD9483 internal reference, VREF OUT (Pin 97), provides

a simple, cost effective reference for many applications. It exhib-

its reasonable accuracy and excellent stability over power supply

and temperature variations. The reference output can be used to

set the three ADCs’ gain and offset. The reference is capable of

providing up to 1 mA of additional current beyond the require-

ments of the AD9483.

As the ADC gain and offset are set by the reference inputs,

some applications may require a reference with greater accuracy

or temperature performance. In these cases, an external refer-

ence may be connected directly to the VREF IN pins. VREF

OUT, if unused, should be left floating. Note, each of the three

VREF IN pins will require up to 1 mA of current.

Modes of Operation

The AD9483 has three modes of operation, Single Channel

output mode, and a Dual Channel output mode with two pos-

sible data formats, interleaved or parallel. Two pins control which

mode of operation the chip is in, Pin 74 Output Mode Select

(OMS) and Pin 75 Interleaved/Parallel Select (I/P). Table II

shows the configuration required for each mode.

Table II. Output Mode Selection

MODE

OMS

I/P

Dual Channel—Parallel

LOW

Dual Channel—Interleaved

LOW

HIGH

Single Channel

HIGH

DON’T CARE

Demuxed Output Mode

In demuxed mode, (Pin 74 OMS = LOW), the ADC output

data are alternated between the two output ports (Port A and

Port B). This limits the data output rate to 1/2 the rate of

ENCODE, and facilitates conversion rates up to 140 MSPS.

Demuxed output mode is recommended for guaranteed opera-

tion above 100 MSPS, but may be enabled at any specified

conversion rate.

Two data formats are possible in Dual Channel output mode,

parallel data out and interleaved data out. Pin 75 I/P should be

LOW for parallel format and HIGH for interleaved format.

Figures 1 and 2 show the timing requirements for each format.

Note that the Data Sync input, (DS), is required in Dual Chan-

nel output mode for both formats. The section on Data Sync

describes the requirements of the Data Sync input.

As shown in Figures 1 and 2, when using the interleaved data

format, a sample is taken on an ENCODE rising edge N. The

resulting data is produced on an output port following the fifth

rising edge of ENCODE after the sample was taken, (five pipe-

line delays). The following sample, (N+1), will be produced on

the opposite port, also five pipeline delays after it was taken.

The state of CLKOUT when the sample was taken will deter-

mine out of which port the data will come. If CLKOUT was

LOW, the data will come out Port A. If CLKOUT was HIGH,

the data will come out Port B.

In order to achieve parallel data format on the two output data

ports, the data is internally aligned. This is accomplished by

adding an extra pipeline delay to just the A Data Port. Thus,

data coming out Port A will have six pipeline delays and data

coming out Port B will have five pipeline delays. As with the

interleaved format, the state of Data Sync when a sample is

taken will determine out of which port the data will come. If

CLKOUT was LOW, the data will come out Port A. If CLK-

OUT was HIGH, the data will come out Port B.

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