AD9760-EB datasheet(15/23 Pages) AD

15 / 23 page

AD9760

–15–

REV. B

Note, the clock input could also be driven via a sine wave that is

centered around the digital threshold (i.e., DVDD/2), and

meets the min/max logic threshold. This will typically result in a

slight degradation in the phase noise, that becomes more notice-

able at higher sampling rates and output frequencies. Also, at

higher sampling rates, the 20% tolerance of the digital logic

threshold should be considered since it will affect the effective

clock duty cycle and subsequently cut into the required data

setup and hold times.

SLEEP MODE OPERATION

The AD9760 has a power-down function that turns off the out-

put current and reduces the supply current to less than 8.5 mA

over the specified supply range of 2.7 V to 5.5 V and tempera-

ture range. This mode can be activated by applying a logic level

“1” to the SLEEP pin. This digital input also contains an active

pull-down circuit that ensures that the AD9760 remains enabled

if this input is left disconnected. The SLEEP input with active

pull-down requires <40

µA of drive current.

The power-up and power-down characteristics of the AD9760

are dependent upon the value of the compensation capacitor

connected to COMP1. With a nominal value of 0.1

µF, the

AD9760 takes less than 5

µs to power down and approximately

3.25 ms to power back up. Note, the SLEEP MODE should not

be used when the external control amplifier is used as shown in

Figure 45.

POWER DISSIPATION

The power dissipation, PD, of the AD9760 is dependent on

several factors that include: (1) AVDD and DVDD, the power

supply voltages; (2) IOUTFS, the full-scale current output; (3)

fCLOCK, the update rate; (4) and the reconstructed digital input

waveform. The power dissipation is directly proportional to the

analog supply current, IAVDD, and the digital supply current,

IDVDD. IAVDD is directly proportional to IOUTFS as shown in Fig-

ure 47 and is insensitive to fCLOCK.

IOUTFS – mA

220

141618

Figure 47. IAVDD vs. IOUTFS

Conversely, IDVDD is dependent on both the digital input wave-

form, fCLOCK, and digital supply DVDD. Figures 48 and 49

show IDVDD as a function of full-scale sine wave output ratios

(fOUT/fCLOCK) for various update rates with DVDD = 5 V and

DVDD = 3 V, respectively. Note how IDVDD is reduced by more

than a factor of 2 when DVDD is reduced from 5 V to 3 V.

RATIO (fOUT/fCLK)

0.01

0.1

5MSPS

25MSPS

50MSPS

100MSPS

125MSPS

Figure 48. IDVDD vs. Ratio @ DVDD = 5 V

RATIO (fOUT/fCLK)

0.01

0.1

5MSPS

25MSPS

50MSPS

100MSPS

125MSPS

Figure 49. IDVDD vs. Ratio @ DVDD = 3 V

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