REV. A

AD9822

–12–

CIRCUIT OPERATION

Analog Inputs—CDS Mode

Figure 8 shows the analog input configuration for the CDS

mode of operation. Figure 9 shows the internal timing for the

sampling switches. The CCD reference level is sampled when

CDSCLK1 transitions from high to low, opening S1. The CCD

data level is sampled when CDSCLK2 transitions from high to

low, opening S2. S3 is then closed, generating a differential output

voltage representing the difference between the two sampled levels.

The input clamp is controlled by CDSCLK1. When CDSCLK1

is high, S4 closes and the internal bias voltage is connected to

the analog input. The bias voltage charges the external 0.1

µF

input capacitor, level-shifting the CCD signal into the AD9822’s

input common-mode range. The time constant of the input

clamp is determined by the internal 5 k

Ω resistance and the

external 0.1

µF input capacitance.

AD9822

S1

S2

2pF

S3

2pF

CML

CML

AVDD

4V

S4

5k

1.7k

VINR

OFFSET

0.1 F

CCD SIGNAL

0.1 F

1 F

+

3V

2.2k

6.9k

INPUT CLAMP LEVEL

IS SELECTED IN THE

CONFIGURATION

REGISTER

Figure 8. CDS-Mode Input Configuration (All Three Chan-

nels Are Identical)

CDSCLK1

CDSCLK2

Q3

(INTERNAL)

S1, S4 CLOSED

S1, S4 CLOSED

S2 CLOSED

S2 CLOSED

S3 CLOSED

S3 CLOSED

S3 OPEN

S2 OPEN

S1, S4 OPEN

Figure 9. CDS-Mode Internal Switch Timing

External Input Coupling Capacitors

The recommended value for the input coupling capacitors is

0.1

µF. While it is possible to use a smaller capacitor, this larger

value is chosen for several reasons:

1. Signal Attenuation. The input coupling capacitor creates a

capacitive divider with a CMOS integrated circuit’s input

large relative to the IC’s 10 pF input capacitance in order to

minimize this effect.

2. Linearity. Some of the input capacitance of a CMOS IC is

junction capacitance, which varies nonlinearly with applied

voltage. If the input coupling capacitor is too small, then the

attenuation of the CCD signal will vary nonlinearly with signal

level. This will degrade the system linearity performance.

3. Sampling Errors. The internal 2 pF sample capacitors have

a “memory” of the previously sampled pixel. There is a

sample capacitors for larger pixel-to-pixel voltage swings. As

redistribution error will be less than 1 LSB for a full-scale

pixel-to-pixel voltage swing.

Analog Inputs—SHA Mode

Figure 10 shows the analog input configuration for the SHA

mode of operation. Figure 11 shows the internal timing for the

sampling switches. The input signal is sampled when CDSCLK2

transitions from high to low, opening S1. The voltage on the

OFFSET pin is also sampled on the falling edge of CDSCLK2,

when S2 opens. S3 is then closed, generating a differential out-

put voltage representing the difference between the sampled

input voltage and the OFFSET voltage. The input clamp is

disabled during SHA mode operation.

AD9822

S1

2pF

S3

CML

VINR

INPUT SIGNAL

S2

2pF

CML

OFFSET

RED

VING

GREEN

VINB

BLUE

OPTIONAL DC OFFSET

(OR CONNECT TO GND)

Figure 10. SHA-Mode Input Configuration (All Three

Channels Are Identical)

CDSCLK2

Q3

(INTERNAL)

S1, S2 CLOSED

S1, S2 CLOSED

S3 CLOSED

S3 CLOSED

S3 OPEN

S1, S2 OPEN

Figure 11. SHA-Mode Internal Switch Timing