AD9853

–14–

REV. C

DIGITAL

QPSK/16–QAM

MODULATOR

CONTROL PROCESSOR

SERIAL

CONTROL

BUS

GAIN CONTROL BUS

COUPLING

CIRCUIT AND

LP FILTER

POWER

DOWN

AD9853

DIRECT

CONTROL

LINES

DATA IN

REF

CLOCK IN

PROGRAMMABLE

CABLE DRIVER

AMPLIFIER

AD8320

TO

DIPLEXER

CONTROL

PROCESSOR

Figure 32. Basic Implementation of AD9853 Digital Modulator and AD8320 Programmable Cable Driver Amplifier in

Return-Path Application

RESET

NOTE 1

NOTE

2

NOTE

2

CONTROL BUS

DAC OUT

NOTE 1. DURING THIS INTERVAL ALL CONTROL BUS REGISTERS MUST BE PROGRAMMED.

NOTE 2. DURING THIS INTERVAL THE CONTROL REGISTER (48h) MAY NEED TO BE REPROGRAMMED DUE TO BEING CLEARED

BY THE PRECEDING RESET PULSE.

NOTE 3. THREE RESETS ARE REQUIRED TO ENSURE THAT THE DATA PATH IS ZERO'D.

START UP

SEQUENCE

Figure 31. Recommended Start-Up Sequence

NOTES ON THE RESET FUNCTION:

1. RESET IS ACTIVE LOW

2. RESET ZEROS THE CONTROL REGISTER AT ADDRESS 48 HEX WHICH CAUSES THE FOLLOWING DEFAULT

CONDITION TO EXIST:

A. 6

REFCLK IS DISABLED

B. OUTPUT SPECTRUM IS SET TO I COS+Q SIN

C. DIGITAL PLL POWER-DOWN IS DISABLED

D. PLL POWER-DOWN IS DISABLED

E. DAC PLL POWER-DOWN IS DISABLED

3. SERIAL CONTROL BUS IS RESET AND INITIALIZED.

4. OUTPUTS OF MODULATION ENCODERS ARE SET TO ZERO. THIS ALLOWS THE FIR FILTERS AND

5. THE PREAMBLE IS CLEARED UPON EXECUTION OF THE RESET FUNCTION.