ADF4001 datasheet(4/16 Pages) AD

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REV. 0

ADF4001

–4–

PIN FUNCTION DESCRIPTIONS

Mnemonic

Function

1RSET

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The

nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is

SET

23 5

So, with RSET = 4.7 k

Ω, ICP MAX = 5 mA.

Charge Pump Output. When enabled, this provides

±I

CP to the external loop filter which, in turn, drives the

external VCO or VCXO.

CPGND

Charge Pump Ground. This is the ground return path for the charge pump.

AGND

Analog Ground. This is the ground return path of the prescaler.

5RFINB

Complementary Input to the N Counter. This point must be decoupled to the ground plane with a small

bypass capacitor, typically 100 pF. See Figure 3.

6RFINA

Input to the N Counter. This small signal input is ac-coupled to the external VCO or VCXO.

7AVDD

Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground

plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.

REFIN

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resis-

tance of 100 k

Ω. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator or can be

ac-coupled.

DGND

Digital Ground

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-

state mode. Taking the pin high will power up the device, depending on the status of the power-down bit F2.

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

the 24-bit shift register on the CLK rising edge. This input is a high-impedance CMOS input.

DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is

a high-impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of

the four latches, the latch being selected using the control bits.

MUXOUT

This multiplexer output allows either the Lock Detect, the scaled RF, or the scaled Reference Frequency to

be accessed externally.

DVDD

Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane

should be placed as close as possible to this pin. DVDD must be the same value as AVDD.

Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it

can be set to 5 V and used to drive a VCO or VCXO with a tuning range of up to 5 V.

PIN CONFIGURATIONS

TRANSISTOR COUNT

6425 (CMOS) and 50 (Bipolar).

TOP VIEW

(Not to Scale)

ADF4001

RSET

MUXOUT

DVDD

CPGND

AGND

CLK

DATA

RFINB

RFINA

AVDD

REFIN

DGND

15 MUXOUT

14 LE

13 DATA

12 CLK

CPGND 1

AGND 2

AGND 3

11 CE

RFINB 4

RFINA 5

PIN 1

INDICATOR

TOP VIEW

ADF4001

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