–8–

REV. 0

ADG661/ADG662/ADG663

SD

0.1 F

IN

GND

50

0.1 F

7. Off Isolation

16-Lead TSSOP

(RU-16)

16

9

8

1

0.201 (5.10)

0.193 (4.90)

PIN 1

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256

(0.65)

BSC

0.0433

(1.10)

MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

8°

0°

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Test Circuits (Continued)

8. Channel-to-Channel Crosstalk

SD

0.1 F

GND

50

NC

0.1 F

S

D

50

CHANNEL TO CHANNEL

CROSSTALK = 20

APPLICATION

Figure 9 illustrates a precise, sample-and-hold circuit. An

AD845 is used as the input buffer while the output operational

amplifier is an OP07. During the track mode, SW1 is closed and

Due to switch and capacitor leakage, the voltage on the hold

capacitor will decrease with time. The ADG661/ADG662/

ADG663 minimizes this droop due to its low leakage specifica-

tions. The droop rate is further minimized by the use of a poly-

styrene hold capacitor. The droop rate for the circuit shown is

typically 15

µV/µs.

A second switch SW2, which operates in parallel with SW1, is

included in this circuit to reduce pedestal error. Since both

switches will be at the same potential, they will have a differen-

tial effect on the op amp OP07 which will minimize charge

injection effects. Pedestal error is also reduced by the compensa-

duces the hold time glitch while optimizing the acquisition time.

Using the illustrated op amps and component values, the pedes-

tal error has a maximum value of 5 mV over the

±3 V input

range. The acquisition time is 2.5 ms while the settling time is

1.85

µs.

+5V

–5V

2200pF

75

1000pF

2200pF

ADG661

ADG662

ADG663

SW2

SW1

S

S

D

D

+5V

–5V

AD845

+5V

–5V

OP07

Figure 9. Accurate Sample-and-Hold