ADMC200

REV. B

–12–

Table VII. System Status Register (SYSSTAT)

1

RESET

Bit

Function

Default

0

A/D Conversion

Completion Interrupt

(1 = True)

0

1

Vector Transformation

Completion Interrupt

(1 = True)

0

4

Rotation Results are Valid

(1 = Valid)

X

2

11

IRQ Generated from This

0

Device (1 = True)

NOTES

Bit 0

A/D Conversion Completion Interrupt. This register

is set to 1 when the A/D conversion process has com-

pleted and ADC interrupts have been enabled in the

SYSCTRL register.

Bit 1

Interrupt Status. This register is set to 1 when the

Vector Transformation is completed and the Vector

Transformation completion interrupts have been

enabled.

Bit 4

This bit is set to 1 when the rotation results are valid.

Bit 11

If any interrupt source on the ADMC200 occurs, then

this bit is set to 1.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

68-Lead Plastic Leaded Chip Carrier (PLCC)

(P-68A)

9

PIN 1

IDENTIFIER

10

61

60

26

27

44

43

TOP VIEW

(PINS DOWN)

0.995 (25.27)

0.985 (25.02)

SQ

0.954 (24.23)

0.950 (24.13)

SQ

0.019 (0.48)

0.017 (0.43)

0.050

(1.27)

TYP

0.925 (23.50)

0.895 (22.73)

0.029 (0.74)

0.027 (0.69)

0.104 (2.64) TYP

0.175 (4.45)

0.169 (4.29)

BOTTOM VIEW

(PINS UP)

PIN 1

IDENTIFIER

Table VI. SYSCTRL Analog Input Channel Selection

Bit 3

Bit 4

Channels Converted

Mode

0

0

V, W (Default)

Two/Three Phase

0

1

V, W, AUX

Two/Three Phase

1

0

U, V, W

Three/Three Phase

1

1

U, V, W, AUX

Three/Three Phase

Bit 8

IRQ Pin Format—Edge or Level Interrupt Selection.

If Bit 8 is set to 0, then an interrupt will cause a pulse

of one system clock to be generated on the

IRQ pin.

If Bit 8 is set to 1, then an interrupt causes the

IRQ

output to go LOW (logic 0). The

IRQ output pin

will remain LOW until the SYSSTAT register is read.

Bit 10

If Bit 10 is set to 1, then the reverse Park transforma-

tion will be formed in 3/3 mode. For Forward

transformations, this bit must be set to 1.