ADMC330BST datasheet(15/20 Pages) AD

15 / 20 page

ADMC330

–15–

REV. 0

A software controlled full peripheral reset (including the watch-

dog timer) is achieved by toggling the DSP FL2 flag from 1 to 0

to 1 again.

MEMORY MAP

The ADMC330 has two types of memory: data memory and

program memory. Program RAM starts at 0x0000, while the

program ROM area starts at 0x800. The data RAM starts at

0x3800 while the peripherals are mapped to a data memory

block starting at 0x2000.

Table V. Program Memory

0x0000–0x002F

Interrupt Vector Table

0x0030–0x07FF

User Program Space

0x0800–0x0BFF

ROM Monitor

0x0C00–0x0FFF

ROM Math Utilities

Table VI. Data Memory

0x2000–0x201F

Peripherals

0x3800–0x3B8F

User Data Space

0x3B90–0x3BFF

Reserved for ROM Monitor Use

ADMC330 Registers

Some registers store values. For example, AX0 stores an ALU

operand; I4 stores a DAG2 pointer. Other registers consist of

control bits and fields, or status flags. For example, ASTAT

contains status flags from arithmetic operations, and fields in

DWAIT control the numbers of wait states for different zones of

data memory.

A secondary set of registers in all computational units allows a

single-cycle context switch.

The bit and field definitions for control and status registers are

given in the rest of this section, except for IMASK, ICNTL and

IFC, which are defined earlier in this data sheet. The system

control register, timer registers and SPORT control registers are

all mapped into data memory; that is, registers are accessed by

reading and writing data memory locations rather than register

names. The particular data memory address is shown with each

memory-mapped register.

Biased Rounding

A new mode allows biased rounding in addition to the normal

unbiased rounding. When the BIASRND bit is set to 0, the

normal unbiased rounding operations occur. When the BIASRND

bit is set to 1, biased rounding occurs instead of the normal unbi-

ased rounding. When operating in biased rounding mode all

rounding operations with MR0 set to 0x8000 will round up,

rather than only rounding odd MR1 values up. For example:

MR value before RND biased RND result

unbiased RND result

00-0000-8000

00-0001-8000

00-0000-8000

00-0001-8000

00-0002-8000

00-0000-8001

00-0001-8001

00-0002-8001

00-0000-7FFF

00-0001-7FFF

This mode only has an effect when the MR0 register contains

0x8000; all other rounding operation work normally. This mode

was added to allow more efficient implementation of bit speci-

fied algorithms that specify biased rounding, such as the GSM

speech compression routines. Unbiased rounding is preferred

for most algorithms.

Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer

Control register.

INSTRUCTION SET DESCRIPTION

The ADMC330 assembly language instruction set has an

algebraic syntax that was designed for ease of coding and read-

ability. The assembly language, which takes full advantage of the

processor’s unique architecture, offers the following benefits:

• The algebraic syntax eliminates the need to remember

cryptic assembler mnemonics. For example, a typical arith-

metic add instruction, such as AR = AX0 + AY0, resembles a

simple equation.

• Every instruction assembles into a single, 24-bit word that can

execute in a single instruction cycle.

• The syntax is a superset ADSP-2100 Family assembly lan-

guage and is completely source and object code compatible

with other family members.

• Sixteen condition codes are available. For conditional jump,

call, return or arithmetic instructions, the condition can be

checked and the operation executed in the same instruction

cycle.

• Multifunction instructions allow parallel execution of an arith-

metic instruction with up to two fetches or one write to pro-

cessor memory space during a single instruction cycle.

Consult the ADSP-2100 Family User’s Manual for a complete

description of the syntax and an instruction set reference with

particular reference to the ADSP-2171 device.

Interrupt Enable

The ADMC330 supports an interrupt enable instruction. Inter-

rupts are enabled by default at reset. The instruction source

code is specified as follows:

Syntax:

ENA INTS;

Description:

Executing the ENA INTS instruction allows

all unmasked interrupts to be serviced again.

Interrupt Disable

The ADMC330 supports an interrupt disable instruction. The

instruction source code is specified as follows:

Syntax:

DIS INTS;

Description:

Reset enables interrupt servicing. Executing

the DIS INTS instruction causes all inter-

rupts to be masked without changing the

contents of the IMASK register. Disabling

interrupts does not affect the autobuffer cir-

cuitry, which will operate normally whether

or not interrupts are enabled. The disable

interrupt instruction masks all user interrupts

including the power-down interrupt.

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