ADMC331

–27–

REV. B

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

00

0

0

0000

00

0

0

00

0

0

2

PWMDT

SECONDS

PWMDT (R/W)

DM (0x2009)

PWMDT

PWMTM (R/W)

DM (0x2008)

PWMTM

2

PWMTM

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0 = ENABLE

1 = DISABLE

CH OUTPUT DISABLE

CL OUTPUT DISABLE

BH OUTPUT DISABLE

BL OUTPUT DISABLE

AH OUTPUT DISABLE

AL OUTPUT DISABLE

0 = NO CROSSOVER

1 = CROSSOVER

A CHANNEL CROSSOVER

B CHANNEL CROSSOVER

C CHANNEL CROSSOVER

DM (0x200F)

PWMSEG (R/W)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

00

00

0

0

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

01

0

0

011

1

00

0

0

00

0

0

PWMSYNCWT (R/W)

DM (0x2060)

PWMSYNCWT

TPWMSYNC,ON =

PWMSYNCWT + 1

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

00

0

0

0000

00

00

000

0

PWMSWT (R/W)

DM (0x2061)

Figure 16. Configuration of ADMC331 Registers

Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these

bits should always be written as shown.