ADMC401BST datasheet(42/60 Pages) AD

42 / 60 page

REV. B

ADMC401

–42–

WATCHDOG TIMER

OVERVIEW

The watchdog timer is used as a protection mechanism against

unintentional software events causing the DSP to become stuck

in infinite loops. It can be used to cause a complete DSP and

peripheral reset in the event of such a software error. The watch-

dog timer consists of a 16-bit timer that is clocked at the CLKIN

rate, tCKI.

The watchdog timer is disabled after a master reset (

RESET =

LO). This also resets the WDFLAG bit in the SYSSTAT regis-

ter. The watchdog timer is enabled by writing a TIMEOUT value

to the WDTIMER register. Once the watchdog timer has been

initialized, the timer is decremented at the CLKIN rate. In

order to prevent a watchdog timer trip, it is necessary to write

again to the WDTIMER register. For all writes to the WDTIMER

value is written. The act of writing to the WDTIMER register

automatically reloads the initial TIMEOUT value. If the watch-

dog timer is not rewritten to after an interval:

TWDT = WDTIMER

× tCKI

the watchdog timer will decrement to zero and a watchdog trip

will be generated. In this case, a complete reset of the DSP core

and motor control peripherals (except the watchdog timer

itself) is initiated and Bit 1 of the SYSSTAT register (WDFLAG)

is set. Following a reset, the DSP core can determine if the reset

was caused by a watchdog trip (and if so take appropriate ac-

tion) or if it was due to the normal reset sequence. The watchdog

timer remains disabled while the WDFLAG is set to prevent

continuous watchdog trips. The watchdog timer can be restarted

and the WDFLAG reset by writing a nonzero TIMEOUT value

to the WDTIMER register. The WDFLAG will be reset, but

the watchdog timer will remain disabled if 0x0000 is written to

the WDTIMER register.

The watchdog timer is only reset by a low input on the

RESET

pin. The watchdog circuit is not reset by a software controlled

Peripheral Reset.

PROGRAMMABLE INTERRUPT CONTROLLER

OVERVIEW

The ADMC401 uses the

IRQ2 pin of the DSP core to generate

a peripheral interrupt. There are multiple sources of peripheral

interrupts, e.g., the ADC block, PIO block, EIU block, ETU

block and PWM block. A Programmable Interrupt Controller

(PIC) is used to avoid a software latency in determining the

source of the interrupt. With the occurrence of an interrupt

from the peripheral blocks, the PIC block generates an address

that points to the corresponding vector address in the DSP vector

table. The PIC consists of an output register, PICVECTOR,

that contains a pointer to an entry in the DSP vector table.

During normal operation, an interrupt service routine (ISR)

located at vector address 0x0004 (or the

IRQ2/peripheral inter-

rupt) jumps to the address pointed to by the PICVECTOR

0x0004 is automatically placed there by the internal ROM code

when MMAP = BMODE = 1.

The vector addresses between 0x00 and 0x2C are reserved

for the DSP core interrupts. The vector table addresses from

PM(0x30) to PM(0x58) are reserved for use by peripheral inter-

rupt service routines. Each vector address occupies four addresses

of PM. The priority of the peripheral interrupts is fixed in hard-

ware. The ISR at address PM(0x30) has the highest priority

whereas the ISR at address PM(0x58) has the lowest.

In the case of multiple simultaneous interrupts, the PIC will

load the PICVECTOR register with the interrupt that has the

highest priority. Between reads of the PICVECTOR register

(while the DSP is servicing other interrupts for example)

PICVECTOR is updated with the highest priority of any periph-

eral interrupts. This ensures that when the

IRQ2 is reasserted,

the highest priority interrupt that occurred since the last reading

of the PICVECTOR register is now waiting to be serviced.

When PICVECTOR is read, if another interrupt is pending in

the PIC, then the

IRQ2 line to the DSP remains LO and no edge

will be seen. In order to catch all interrupts,

IRQ2 interrupts

should be configured as level sensitive in the ICNTL register.

The four least significant PIO pins are assigned unique vector

addresses. An interrupt on any of the remaining eight lines

(PIO4 to PIO11) will trigger a separate fifth PIO interrupt that

has its own vector address. The PIOFLAG register can be read

to determine the exact source of this fifth interrupt. An 11-bit

PICMASK register can be used to enable or disable any or all of

the eleven peripheral interrupt sources. The program memory

address reserved for each of the interrupts is summarized in

Table VII.

Table VII. Interrupt Vector Addresses

Function

Vector Address

RESET Startup (or Power Up with

PUCR = 1)

0x00 (Highest Priority)

Power-Down (Nonmaskable)

0x2C

ADC End-of-Conversion Interrupt

0x30

PWMSYNC Interrupt

0x34

EIU Loop Timer Timeout Interrupt

0x38

PIO4 to PIO11 Interrupt

0x3C

EIU Counter Error Interrupt

0x40

ETU Interrupt

0x44

PIO0 Interrupt

0x48

PIO1 Interrupt

0x4C

PIO2 Interrupt

0x50

PIO3 Interrupt

0x54

PWM Trip Interrupt

0x58

SPORT0 Transmit

0x10

SPORT0 Receive

0x14

Software Interrupt 1

0x18

Software Interrupt 0

0x1C

SPORT1 Transmit (or

IRQ1)

0x20

SPORT1 Receive (or

IRQ0)

0x24

Interval Timer Interrupt

0x28 (Lowest Priority)

Interrupt Masking

Interrupt masking (or disabling) is controlled by the IMASK

registers contain individual bits that must be set to enable the

various interrupt sources. It is important to remember that if

any peripheral interrupt is to be enabled both the

IRQ2

interrupt enable bit (Bit 9) of the IMASK register and the

appropriate bit of the PICMASK register must be set. The

configuration of both the IMASK and PICMASK registers of

the ADMC401 is shown at the end of the data sheet.

ADMC401BST Datasheet(PDF) 42 Page - Analog Devices

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