–8–

Phase One: When the input voltage is equal to 3.7 V or higher,

the ADP3000 is off and the ADP3302 operates on its own to

regulate the output voltage. At this phase, current is flowing into

the input pins of the ADP3302 via the inductor L1 and the

Schottky diode. At the same time, the ADP3000 is set into sleep

mode by pulling the FB pin (via R9 and R10 resistor divider

network) to about 10% higher than its internal reference which

is set to be 1.245 V.

Phase Two: As the input voltage drops below 3.7 V, the

decreasing input voltage causes the voltage of the FB pin to be

within 5% of the 1.245 V reference. This triggers the ADP3000

to turn on, providing a 3.4 V regulated output to the inputs of

the ADP3302. The ADP3000 continues to supply the 3.4 V

regulated voltage to the ADP3302 until the input voltage drops

below 2.5 V.

Phase Three: When the input voltage drops below 2.5 V, the

ADP3302 will shut down and the ADP3000 will go into sleep

mode. With the input voltage below 2.5 V, the resistor divider

network, R1 and R2, applies a voltage that is lower than the

ADP3000’s internal 1.245 V reference voltage to the SET pin.

causes the ADP3302 to go into shutdown directly and Q1 to

turn on and pull the FB pin 10% or higher than the internal

1.245 V reference voltage. With the FB pin pulled high, the

ADP3000 goes into sleep mode.

80

75

70

65

SHDN IQ = 500µA

2.6

3.0

3.4

3.8

4.2

(V)

Figure 21. Typical Efficiency of the Circuit of Figure 20

Refer to Figure 20. R9 and R10 set the output voltage of the

ADP3000. R1, R2, and R3 set the shutdown threshold voltage

for the circuit. For further details on the ADP3000, please refer

to the ADP3000 data sheet.

Supply Sequencing Circuit

Figure 22 shows a simple and effective way to achieve sequenc-

ing of two different output voltages, 3.3 V and 5 V, in a mixed

supply voltage system. In most cases, these systems need careful

sequencing for the supplies to avoid latchup.

At turn-on, D1 rapidly charges up C1 and enables the 5 V out-

put. After a R2-C2 time constant delay, the 3.3 V output is

enabled. At turn-off, D2 quickly discharges C2 and R3 pulls

SD1 low, turning off the 3.3 V output first. After a R1-C1 time

constant delay, the 5 V output turns off.

ADP3302

2

OUT1

IN

1

8

ERR

3.3V

C5

1µF

5

GND

SD1

IN

OUT2

5.0V

SD2

C2

0.01µF

C1

0.01µF

C4

0.5µF

C3

0.5µF

ON/OFF

3.3V

D2

D1

R2

220k

Ω

R1

220k

Ω

D3

R3

330k

Ω

4

7

6

3

Figure 22. Turn-On/Turn-Off Sequencing for Mixed Supply

Voltages

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Pin SOIC

(SO-8)

0.1968 (5.00)

0.1890 (4.80)

8

5

4

1

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.1574 (4.00)

0.1497 (3.80)

0.0688 (1.75)

0.0532 (1.35)

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0500

(1.27)

BSC

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8

°

0

°

0.0196 (0.50)

0.0099 (0.25)

x 45

°

REV. 0

ADP3302

3V

100mA

3V

100mA

1µF

6V

(MLC)

1µF

6V

(MLC)

C4

C5

IN

IN

SD

GND

ADP3302

C3

100µF

10V

AVX-TPS

R9

348k

Ω

1%

R10

200k

Ω

1%

IN5817

L1

6.6µF

(SUMIDA–CDRH62)

Q1

2N2907

R5

330k

Ω

R6

100k

Ω

R8

10k

Ω

R7

90k

Ω

C2

33nF

R4

120k

Ω

R1

100k

Ω

C1

100µF

10V

AVX-TPS

R3

1M

Ω

R2

90k

Ω

2.5V

→ 4.2V

SET

GND SW2

SW1

FB

ADP3000