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ADSP-2183 Datasheet(PDF) 1 Page - Analog Devices |
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ADSP-2183 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 31 page  FUNCTIONAL BLOCK DIAGRAM SERIAL PORTS MEMORY FLAGS PROGRAMMABLE I/O BYTE DMA CONTROLLER PROGRAM MEMORY DATA MEMORY EXTERNAL ADDRESS BUS EXTERNAL DATA BUS DMA BUS INTERNAL DMA PORT TIMER SPORT 1 SPORT 0 ADSP-2100 BASE ARCHITECTURE SHIFTER MAC ALU ARITHMETIC UNITS POWERDOWN CONTROL PROGRAM SEQUENCER DAG 2 DATA ADDRESS GENERATORS PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA DAG 1 a DSP Microcomputer ADSP-2183 FEATURES PERFORMANCE 19 ns Instruction Cycle Time from 26.32 MHz Crystal @ 3.3 Volts 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 300 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP-2100 Family Code Compatible, with Instruction Set Extensions 80K Bytes of On-Chip RAM, Configured as 16K Words On-Chip Program Memory RAM 16K Words On-Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 128-Lead LQFP, 144-Ball Mini-BGA SYSTEM INTERFACE 16-Bit Internal DMA Port for High Speed Access to On-Chip Memory 4 MByte Memory Interface for Storage of Data Tables and Program Overlays 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers I/O Memory Interface with 2048 Locations Supports Parallel Peripherals Programmable Memory Strobe and Separate I/O Memory Space Permits “Glueless” System Design Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling ICE-Port™ Emulator Interface Supports Debugging in Final Systems REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ICE-Port is a trademark of Analog Devices, Inc. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 GENERAL DESCRIPTION The ADSP-2183 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2183 combines the ADSP-2100 family base architec- ture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. The ADSP-2183 integrates 80K bytes of on-chip memory con- figured as 16K words (24-bit) of program RAM, and 16K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2183 is available in 128-lead LQFP, and 144-Ball Mini-BGA packages. In addition, the ADSP-2183 supports new instructions, which include bit manipulations—bit set, bit clear, bit toggle, bit test— new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory trans- fers and global interrupt masking, for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2183 operates with a 19 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-2183’s flexible architecture and comprehensive instruction set allow the processor to perform multiple opera- tions in parallel. In one processor cycle the ADSP-2183 can: • Generate the next program address • Fetch the next instruction • Perform one or two data moves • Update one or two data address pointers • Perform a computational operation |
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