ADV7171 datasheet(29/55 Pages) AD

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ADV7170/ADV7171

–29–

REV. 0

TC01

TC00

TC07

TC02

TC04

TC03

TC05

TC06

TTXREQ RISING EDGE CONTROL

TC07 TC06

TC05 TC04

0 PCLK

1 PCLK

" PCLK

14 PCLK

15 PCLK

TTXREQ FALLING EDGE CONTROL

TC03 TC02

TC01 TC00

0 PCLK

1 PCLK

" PCLK

14 PCLK

15 PCLK

Figure 50. Teletext Control Register

CGMS CRC CHECK

CONTROL

DISABLE

ENABLE

C/W04

WIDE SCREEN SIGNAL

CONTROL

DISABLE

ENABLE

C/W07

C/W06

C/W05

C/W04

C/W03

C/W02

C/W01

C/W00

CGMS ODD FIELD

CONTROL

DISABLE

ENABLE

C/W05

C/W03–C/W00

CGMS DATA BITS

CGMS EVEN FIELD

CONTROL

DISABLE

ENABLE

C/W06

Figure 51. CGMS_WSS Register 0

C/W0 BIT DESCRIPTION

CGMS Data Bits (C/W03–C/W00)

These four data bits are the final four bits of CGMS data output

stream. Note it is CGMS data ONLY in these bit positions, i.e.,

WSS data does not share this location.

CGMS CRC Check Control (C/W04)

When this bit is enabled (“1”), the last six bits of the CGMS

data, i.e., the CRC check sequence, is calculated internally by

the ADV7170/ADV7171. If this bit is disabled (“0”) the CRC

values in the register are output to the CGMS data stream.

CGMS Odd Field Control (C/W05)

When this bit is set (“1”), CGMS is enabled for odd fields.

Note this is only valid in NTSC mode.

CGMS Even Field Control (C/W06)

When this bit is set (“1”), CGMS is enabled for even fields.

Note this is only valid in NTSC mode.

WSS Control (C/W07)

When this bit is set (“1”), wide screen signaling is enabled. Note

this is only valid in PAL mode.

CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10)

(Address [SR4–SR0] = 17H)

CGMS_WSS register 1 is an 8-bit-wide register. Figure 52

shows the operations under the control of this register.

C/W1 BIT DESCRIPTION

CGMS/WSS Data Bits (C/W15–C/W10)

These bit locations are shared by CGMS data and WSS data. In

NTSC mode these bits are CGMS data. In PAL mode these

bits are WSS data.

CGMS Data Bits (C/W17–C/W16)

These bits are CGMS data bits only.

CGMS_WSS REGISTER 2 C/W1 (C/W27–C/W20)

(Address [SR4–SR0] = 18H)

CGMS_WSS register 2 is an 8-bit-wide register. Figure 53

shows the operations under the control of this register.

C/W2 BIT DESCRIPTION

CGMS/WSS Data Bits (C/W27–C/W20)

These bit locations are shared by CGMS data and WSS data. In

NTSC mode these bits are CGMS data. In PAL mode these

bits are WSS data.

C/W17

C/W16

C/W15

C/W14

C/W13

C/W12

C/W11

C/W10

C/W15–C/W10

CGMS/WSS DATA

C/W17 C/W16

CGMS DATA ONLY

Figure 52. CGMS_WSS Register 1

C/W27

C/W26

C/W25

C/W24

C/W23

C/W22

C/W21

C/W20

C/W27–C/W20

CGMS/WSS DATA

Figure 53. CGMS_WSS Register 2

ADV7171 Datasheet(PDF) 29 Page - Analog Devices

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